Faculty Publications
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Item A Novel PWM Technique for MPPT Tracking of PV-Based Cascaded H-bridge Multi-level Inverter(Institute of Electrical and Electronics Engineers Inc., 2023) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.This paper presents a novel Pulse Width Modulation (PWM) technique designed for a Cascaded H-Bridge (CHB) grid-tied multilevel inverter used in Photovoltaic (PV) systems, featuring a single-stage power conversion. Each inverter's output voltage adopts a quasi-square waveform tailored to correspond with the power generated by the respective solar panel. A key highlight of this technique is its simplicity, avoiding complex implementation. By incorporating the proposed PWM technique into the cascaded H-Bridge inverters, it efficiently optimizes the Maximum Power Point Tracking (MPPT) for each PV panel, regardless of whether the irradiation conditions are uniform or non-uniform, while simultaneously achieving DC capacitor voltage balance. Moreover, employing this PWM technique simplifies the implementation process on a DSP, avoiding unnecessary complexity. © 2023 IEEE.Item Implementation of Sorted Stair-Case Modulation and Sorted Phase Disposition PWM for Grid-Tied Multi-Level Inverter(Institute of Electrical and Electronics Engineers Inc., 2023) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.Integrating a multilevel inverter with the grid provides advantages in high-power and high-voltage applications, including reduced harmonic distortion without a transformer. This paper presents the implementation of Sorted stair-case modulation (SSCM) and Sorted Phase disposition (SPD) Pulse Width Modulation (PWM) techniques for a Grid-Tied Cascaded H-Bridge (CHB) multilevel inverter featuring single-stage power conversion. SSCM and SPD PWM techniques are used to track the MPPT of each PV panel under uniform and non-uniform irradiation conditions if the PV panels are connected to the inverter's input terminals. A centralized current controller has been designed for the Grid-tied multilevel inverter system. Furthermore, a simulation has been developed to compare the power quality of the grid current and voltage between SSCM and SPD-PWM. © 2023 IEEE.Item Implementation of a Novel Nine-Level Quadruple Boosting Inverter(Institute of Electrical and Electronics Engineers Inc., 2024) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.This paper proposes a novel nine-level quadruple-boosting multilevel inverter (MLI) that uses a single DC source and requires only ten power switches, one diode, and three capacitors. This design utilizes switched capacitors (SC) with a common ground (CG), achieving a four-fold voltage boost without needing an extra boost converter. The common grounding mitigates leakage current, making the system more efficient. In this proposed topology, the capacitors are self-balanced. The proposed inverter topology offers several advantages compared to existing nine-level inverters, such as significantly reducing leakage current due to common ground configuration, boosting capability, and using fewer components. MATLAB Simulink simulations demonstrate the superior effectiveness of the proposed nine-level quadruple-boosting MLI. © 2024 IEEE.Item A Novel Five-Level Double-Boost Inverter with Reduced Spike Current(Institute of Electrical and Electronics Engineers Inc., 2024) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.This paper proposes a novel five-level double-boosting multi-level inverter (MLI) that uses a single DC source and requires only six power switches, one diode, and one capacitor. This design enables soft charging of the capacitor by integrating a charging inductor, which helps minimize or completely avoid large inrush or spike currents in the charging pathway. In this proposed topology, the capacitor is self-balanced. The proposed inverter topology offers several advantages compared to existing five-level inverters, such as significantly reducing inrush current, boosting capability, lower total standing voltage (TSV), common ground configuration, higher efficiency, and using fewer components. MATLAB Simulink simulations demonstrate the superior effectiveness of the proposed five-level double-boosting MLI in terms of reducing spike current. © 2024 IEEE.Item Design and implementation of seven-level inverter for grid-tied photovoltaic systems(Taylor and Francis Ltd., 2025) Maheswari, G.; Manjunatha Sharma, K.M.; P, P.Multi-level inverters without transformer coupling are growingly popular for solar uses because of their compact design, minimised voltage stress, and improved efficiency. In this paper, the proposed novel triple-boost 7-level inverter is optimised for seamless integration with the grid. The proposed inverter employs self-regulating switched-capacitors to achieve a threefold voltage amplification, effectively eliminating the need for an independent boost converter stage. This architecture benefits low-voltage PV systems by improving efficiency, reducing cost, and ensuring superior performance. Moreover, the 7-level inverter adopts a common-ground topology, effectively mitigating leakage currents in PV system applications. The paper elaborates on the operational modes of the proposed inverter and the design of a current controller tailored for a grid-tied PV-based seven-level inverter. Additionally, simulation and experimental validation are conducted utilising hardware-in-the-loop (HIL) methods to evaluate system performance. Finally, a comprehensive comparative analysis is presented between the proposed seven-level inverter and existing seven-level inverters, highlighting the advantages of the proposed inverter design. © 2025 Informa UK Limited, trading as Taylor & Francis Group.Item Implementation of a Novel Quadruple-Boost Nine-Level Inverter for Grid-Tied Applications(Springer Nature, 2025) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.This paper proposes a novel transformer-less quadruple-boost nine-level (QBNL) inverter specifically developed for grid-tied applications. Traditional multilevel inverters (MLIs) typically require numerous components and a transformer for grid integration, which increases cost, weight, size, and losses, thereby diminishing overall efficiency. The proposed nine-level quadruple-boost inverter overcomes these challenges by providing a more streamlined design, significantly enhancing system performance and efficiency. The topology of the proposed inverter consists of ten switches, one diode, and three switched capacitors. These capacitors are self-balanced, maintaining voltage levels at Vdc, 2Vdc, and 2Vdc relative to the input voltage. With a reduced component count (10), lower total standing voltage per unit (5.75), lower cost factor, improved efficiency (97.73), and higher power density, this design offers significant advantages over existing nine-level inverters. The proposed inverter has a soft charging circuit at the DC side to reduce the impulse currents, and a common-mode choke is inserted between the inverter output and the grid to reduce leakage current in PV applications. Additionally, the proposed system incorporates a proportional-integral (PI) controller and phase disposition pulse width modulation technique. A comparative analysis between the proposed nine-level quadruple-boost inverter and existing nine-level inverters highlights its superior performance. The effectiveness of the proposed quadruple-boost nine-level inverter is verified through MATLAB Simulink simulations and Experimental Hardware-in-the-Loop (EHIL) testing, confirming its suitability for grid-tied applications. © 2017 Elsevier Inc. All rights reserved. © The Author(s), under exclusive licence to Shiraz University 2025.Item A sorted modified multi-reference PWM technique for solar PV panel companion grid-tied inverters(Springer Science and Business Media Deutschland GmbH, 2025) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.Pulse Width Modulation (PWM) techniques are increasingly vital in solar energy-driven grid-tied companion inverters, significantly enhancing power quality. This paper proposes the Sorted Modified Multireference Pulse Width Modulation (SMMR PWM) technique. The SMMR PWM with a Maximum PowerPoint Tracking (MPPT) control strategy is implemented in a Solar PV Panel Companion Grid-Tied Inverter (SPPCGTI) system featuring single-stage power conversion. In the SPPCGTI system, each inverter's output voltage adopts a quasi-square waveform, where the pulse width correlates with the power generated by the associated solar PV panel. By employing the SMMR PWM technique with the MPPT control strategy in the SPPCGTI system, precise MPPT for each PV panel is achieved, irrespective of uniform or non-uniform irradiation conditions. Additionally, this technique reduces Total Harmonic Distortion (THD) in the AC grid current of the solar PV panel companion inverter (SPPCI) while simultaneously enhancing MPPT efficiency, inverter efficiency [inverter efficiency is less than the Sorted-Staircase Modulation (SSCM) and more than the Sorted PWM (SoPWM)], and reducing settling time compared to the existing techniques like SSCM and SoPWM. The SPPCGTI with the integrated SMMR PWM technique, MPPT algorithm, and current controller is modeled and simulated in MATLAB/Simulink. Experimental testing affirms the outstanding performance of the proposed SMMR PWM technique. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2024.Item Implementation of a novel nine-level double boosting multi-level inverter(Springer Science and Business Media Deutschland GmbH, 2025) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.Switched capacitor multi-level inverter topologies have garnered the attention of industrial power electronics researchers due to their potential in different industrial and renewable energy source applications. This paper proposes a novel nine-level, twofold voltage gain boost (9L2x) inverter designed for photovoltaic (PV) applications, addressing common challenges in transformer-less multi-level grid-tied PV inverters, such as leakage current and output voltage bucking. This design utilizes switched capacitors (SC) with a common ground, achieving a twofold voltage boost without needing an extra boost converter. The proposed topology reduces the active switch count, enhances power density, and lowers costs while ensuring self-balancing SCs and minimizing total standing voltage. The common grounding mitigates leakage current, making the system more efficient. The proposed topology features a diode-inductor circuit at the input DC side to reduce inrush current, decrease capacitor voltage ripples, reduce the total harmonic distortion of the MLI output voltage, and improve efficiency. A proportional-integral controller manages active grid power, and a modulation strategy ensures SC voltage balance. The paper delves into intricate details concerning the inverter’s circuitry, control methodologies, and pulse-width modulation scheme. This nine-level inverter design is thoroughly validated through extensive simulations and practical hardware-in-the-loop experiments. The results consistently affirm the effectiveness and feasibility of this novel inverter, positioning it as a significant advancement over existing nine-level inverters. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2024.Item Novel sorted PWM strategy and control for photovoltaic-based grid-connected cascaded H-bridge inverters(Springer, 2025) Maheswari, G.; Manjunatha Sharma, K.M.; Prabhakaran, P.This paper proposes a novel sorted level-shifted U-shaped carrier-based pulse width modulation (SLSUC PWM) strategy combined with an input power control approach for a 13-level cascaded H-bridge multi-level inverter designed for grid connection, specifically tailored for photovoltaic (PV) systems, which avoids a double-stage power conversion configuration. In this methodology, every inverter generates a quasi-square output voltage waveform with a width that is intricately linked to the output power of its corresponding PV panel. The application of this SLSUC pulse width modulation technique with input power control in a solar energy-based 13-level grid-tied inverter facilitates precise maximum power point (MPP) tracking for each of the PV panels under uniform and non-uniform irradiation conditions and ensures the consistent maintenance of capacitor voltage balance. Moreover, this novel SLSUC PWM method for 13-level inverters offers a range of benefits, including a low total harmonic distortion (THD) in the output voltage of the multi-level inverter and higher inverter and MPPT efficiencies over the existing PWM techniques. To verify the efficacy of the proposed control method over existing techniques, a PV-based grid-connected multi-level inverter with the proposed control strategy undergoes modeling and simulation using MATLAB/Simulink. Then, experimental hardware-in-the-loop (EHIL) testing is conducted to confirm and evaluate its effectiveness. © The Author(s) under exclusive licence to The Korean Institute of Power Electronics 2024.Item A Novel Seven-Level Triple-Boost Inverter for Grid-Integrated Photovoltaic Systems(Springer, 2025) Maheswari, G.; Manjunatha Sharma, K.M.; P, P.Transformer-less switched-capacitor-based multilevel inverters (TL-SCMLIs) are increasingly preferred for photovoltaic (PV) applications due to their voltage boosting capability, high efficiency, reduced dv/dt stress, and lower cost. However, existing SC-based multi-level inverters often require more components, suffer from leakage currents, have lower boost gain capability, have higher PU total standing voltage, and exhibit lower efficiency. To address these challenges, this paper proposes a novel seven-level switched-capacitor (SC)-based TL-MLI with higher voltage boosting gain and a common ground (CG) configuration for improved performance in grid-tied PV applications. A proportional-integral (PI) controller is designed for the grid-tied seven-level PV inverter, and its performance is evaluated through simulation studies and hardware-in-the-loop (HIL) experimental verification. Finally, a detailed comparative analysis with existing multi-level inverters highlights the proposed seven-level inverter’s advantages, including leakage current reduction, high boost gain, lower cost, lower PU total standing voltage, lower voltage stress, lower peak inverse voltage, and improved efficiency. The total harmonic distortion (THD) of the grid current is less than 5% for the proposed grid-tied seven-level inverter. © The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd. 2025.