Faculty Publications

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Author: search.filters.author.Laxminidhi, T.

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    Energy efficient 1.8 V step down DC/DC converter in 0.18 μm CMOS technology with optimized silicon area
    (2011) Panse, P.; Laxminidhi, T.
    We present a power efficient DC to DC Converter to step down unregulated DC voltage source of 2.7-3.6 V to the regulated 1.8 V DC. The DC to DC Converter, constituted here, is designed for the load current range of 0 to 100 mA. It offers the output voltage ripple and the steady state error less than 1% of the nominal load voltage. The step down converter switches at the frequency of 5 MHz causing substential reduction in the size of the filter inductor and capacitor. This reduction is expoilted to achieve good transient response in case of sudden load change. The Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) switching is used to stipulate approximately 88% of power effiecieny over almost entire range of the load current. This paper also gives mathematical foundation to determine optimum size for a power switch in order to balance out the swiching loss and the ON state loss of the switch under high load condition thereby it redeems the silicon real estate. © 2011 IEEE.
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    Low power fully differential, feed-forward compensated bulk driven OTA
    (2011) Rekha, S.; Laxminidhi, T.
    A low voltage, low power bulk driven Operational Transconductance Amplifier (OTA) is designed in 180 nm CMOS Technology. The OTA employs feed-forward compensation achieving open loop DC gain of 44.05 dB, 3 dB bandwidth of 408 kHz, Unity Gain Bandwidth (UGB) of 9.07 MHz. OTA is stable with phase margin of 45° and a gain margin of 66 dB for a pure capacitive load of 1 pF. OTA operates on 0.5 V supply consuming a power of 30 μW. © 2011 IEEE.
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    On-chip 1.8 V step down DC/DC converter with 94% power efficiency
    (2011) Panse, P.; Laxminidhi, T.
    We present a DC to DC Converter to step down an unregulated DC voltage source of 2.7 - 3.6 V to a regulated 1.8 V DC with peak power efficiency of 94%. The DC to DC Converter, constituted here, is designed for the load current range of 0 to 100 mA. The converter uses a variable switching frequency control method to adjust the power efficiency as well as the ripple to the optimum value as per the load conditions. This control mechanism is implemented by a delta modulator which makes the switching frequency load dependent. The simplicity of the delta modulator causes the silicon real estate as well as the power salvage. It makes the design highly power proficient enabling it to achieve the efficiency greater than the conventional PWM based DC to DC converter. The design, proposed here, procures efficiency of approximately 90% at and above 20% of the full load, and thereby maintains the flat efficiency curve almost over the entire load range. © 2011 IEEE.
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    A 0.5 V, 20 μw pseudo differential 500 kHz Gm-C low pass filter in 0.18 μm CMOS technology
    (2012) Vasantha, M.H.; Laxminidhi, T.
    Scaling of supply voltage due to shrinking in the device sizes has lead to bulk driven circuit techniques specially for analog circuits that operate at low supply voltages. In this paper we present a bulk driven pseudo differential low power, continuous time Cochlea 2 nd order Butterworth low pass filter operating at a supply voltage of 0.5 V. The filter uses Gm-C technique in 0.18 μm n-well standard CMOS process and has a bandwidth of 500 kHz. Simulations results have shown that the filter offers a dynamic range of 48 dB while consuming a power of 20 μW. Simulated Figure of Merit (FOM) is found to be 0.52 fJ and is found to be the lowest among similar low voltage filters found in literature. The percentage change in transconductance is less than μ5% for temperature variation of 0-70°C at 0.5 V supply voltage and across five process corners. © 2012 IEEE.
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    A 0.5V 300μW 50MS/s 180nm 6bit Flash ADC using inverter based comparators
    (2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.
    This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 μW. © 2012 Pillay Engineering College.
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    0.5 V, 36μW Gm-C butterworth low pass filter in 0.18μm CMOS process
    (2012) Vasantha, M.H.; Laxminidhi, T.
    This paper presents a low voltage, low power continuous-time (G m-C) 4th order low pass Butterworth filter with a 3-dB bandwidth of 1MHz and capable of operating at supply voltage as low as 0.5V in 0.18 μm. The filter uses bulk-driven technique for achieving the necessary head-room. The simulation results show that the filter has a peak-to-peak signal swing of 1.2V (differential) for 1% THD and a dynamic range of 54 dB. The power consumed by the filter is 36μW when operating at a voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ and is found to be lowest among the similar filters found in the literature. © 2012 IEEE.
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    A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC
    (2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.
    This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.
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    Switched inverter comparator based 0.5 v low power 6 bit Flash ADC
    (2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.
    This paper presents an ultra low power 6 bit Flash ADC designed in 180 nm CMOS technology for ultra low power applications. The design uses inverter based comparators to reduce the silicon area and power requirement. A novel clock delaying technique is used to power on the three stages of the comparator which work in series. This reduces the power consumption and increases speed of operation. Fat tree architecture is used to design the digital encoder. The power supply used for the design is 0.5 V and the sampling rate is 50 MS/s. The design consumes ultra low power of 600 μW and spans a very small area of 0.164 mm2. In literature this is found to be the lowest for 6 bit ADCs in 180 nm with sampling frequency of 5 MS/s or above. The SNDR remains above 31.5 dB in the whole input frequency range of 0 to 25 MHz. The ADC has maximum DNL of 0.85 LSB and maximum INL of 1 LSB. The FOM of the ADC is found to be 0.39 pJ/conv. © 2012 IEEE.
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    0.5 V, low power, 1 MHz low pass filter in 0.18 μm CMOS process
    (2012) Vasantha, M.H.; Laxminidhi, T.
    In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 μm is achieved. In order to achievenecessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common modefeedback(CMFB) circuit sets the output common mode voltageof transconductor. The simulation results show that the filter has a dynamic range of 54 dB and consumes a total power of 36 μW when operating at a supply voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ, lowest among similar low-voltage filters found in the literature. The simulation result show that the 3-dB bandwidth variation for process, voltage and temperature is less than ±10%. © 2012 IEEE.
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    Effect of finite gain and bandwidth of feed-forward compensated OTA on active-RC integrators: A case study
    (2012) Rekha, S.; Laxminidhi, T.
    This paper analyses the effect of finite gain-bandwidth of the operational transconductance amplifiers (OTAs) on active-RC integrators. A feed-forward compensated OTA is taken as the building block of active-RC integrator. A mathematical analysis is carried out on a first order low-pass active-RC filter designed in 180 nm CMOS technology to operate at a supply voltage of 0.5 V. A non-ideality factor (NIF) has been defined that accounts for the deviation of the response from the ideal. Simulations performed on the transistor level filter justifies the mathematical analysis presented. © 2012 IEEE.