Faculty Publications
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Item An integrated cascode DE power amplifier for RF calibration system towards measurement of bio-sensor applications(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2019) Kumar, R.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.The integrated cascode DE power amplifier for RF calibration system toward measurement of bio-sensor applications is presented in this paper. The proposed architecture includes cascode class-D and class-E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio-sensor application. The inductive ?-shape matching network drives RF input to class-D stage and provides wide bandwidth of operation. While class-E stage with T-shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of ?50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio-sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class-E consuming area of 38% and class-D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V. © 2018 Wiley Periodicals, Inc.Item A compact and efficient graphene FET based RF energy harvester for green communication(Elsevier GmbH, 2020) Singh, N.; Kumar, S.; Kumar Kanaujia, B.K.; Beg, M.T.; Mainuddin, M.; Kumar, S.This paper presents a graphene field effect transistor (FET) based rectenna with substrate-integrated waveguide (SIW) broadband approach for RF energy harvesting application. The proposed structure of integrated rectenna consists of a graphene FET rectifier and an SIW antenna operating in the (S11 < ?10 dB) range of 29–46 GHz. The peak gain of the SIW antenna observed is 8.12 dBi. In addition, a new matched circuit consisting of microstrip line and butterfly stub (without using any lumped elements) is designed. The matched circuit provides a miniaturized block by reducing the size and eliminating parasitic reactance in the integrated rectenna. The proposed rectenna is implemented and fabricated using two superimposed layers: RT/duroid 5880 and graphene substrate with a compatible approach. A measured conversion efficiency of 80.32% is obtained. The dimensions of the proposed antenna and rectifier are 3.2 × 3.2 × 0.4 mm3 and 3.2 × 10 × 0.4 mm3, respectively. The proposed rectenna covers Ka- and Q-band applications and could be a potential candidate for contemporary energy harvesting systems. © 2019 Elsevier GmbHItem Performance of cascode Class-EF?1 PA with built-in techniques for UWB radar toward monitoring of patient actions(Institution of Engineering and Technology kvukmirovic@theiet.org, 2020) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This work proposes a performance of the cascode Class-EF?1 power amplifier (PA) for UWB radar transmitter. The cascode Class-E PA with built-in techniques overcomes the traditional mismatch and provides good performance of PA. Incurs the resonance and switching effect is observed in cascode Class-E PA that compensates for the parasitic effects and provides a wide-impedance range. While design-II includes negative capacitance and inverse Class-F, which achieves a redundant performance of wide bandwidth and power-added efficiency (PAE). Design-II achieves the redundant performance compared with design-I. Both design-I and design-II are implemented and analysed through simulation and experimental results using RF 65 nm Samsung Magnachip Hynix CMOS process. Design-I achieves a wide-impedance bandwidth ranging from 3 to 11.7 GHz with drain efficiency (DE) and maximum PAE of 80 and 73% at the output power of 26.4 dBm. The global efficiency (GE) and error vector magnitude (EVM) of 70 and 5.2% are also achieving for design-I. The redundant performance in design-II achieves wide bandwidth with operating frequency range of 2-13 GHz with maximum DE and PAE of 85 and 76%. For design-II, GE and EVM are investigated as 68 and 4.9% that could validate the accuracy and robustness of the UWB radar. © The Institution of Engineering and Technology 2019Item A compact broadband GFET based rectenna for RF energy harvesting applications(Springer, 2020) Singh, N.; Kumar, S.; Kumar Kanaujia, B.K.; Beg, M.T.; Mainuddin, M.; Kumar, S.In this paper, a compact GFET-based rectifier integrated with a monopole antenna is proposed for wireless energy harvesting applications. The GFET increases impedance bandwidth of the rectifying circuit, thus covering a range of 22.5–27.5 GHz. The sensing antenna is a triangular monopole with truncated corners for realizing circular polarization at the frequencies 24.25 GHz and 27 GHz. By the help of ?/4 transformer, the sensing antenna is matched with the proposed GFET rectifier. The RF-DC conversion efficiency realized is 80% at 5 dBm for the load of 5 K?, and the output DC voltage observed is 6.8 V. The modified ground plane triangular monopole antenna shows a peak gain of 7.8 dBi. The designed rectenna prototype is fabricated and found simulated and measured results are in good agreement. © 2020, Springer-Verlag GmbH Germany, part of Springer Nature.Item Performance of ultra-wide band DCBLNA with suspended strip line radiator for human breast cancer diagnosis medical imaging application(Institution of Engineering and Technology, 2020) Roy, G.M.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I. The performance of SSLIN is evaluated in terms of line capacitance and characteristic impedance by optimising its width. It is observed that best 50 ?n-II. DCBLNA design-II using SSLIN have achieving a desired band of operation ranging from 1.5 to 15.7 GHz and best NF of 0.5 dB. The gain and phase imperfections are simulated to characterise balun networks. The smallest gain imperfection achieved is 0.1 dB at 10 GHz while the simulated phase imperfection turns out to be sufficiently good with 2.35° at 8 GHz. The proposed DCBLNA design-II is implemented and fabricated using RFCMOS 45 nm Taiwan Semiconductor Manufacturing Company (TSMC) process under commercial conditions. The highest figure of merit comes out to be 3.2 that ensures good accuracy of medical imaging for breast cancer diagnosis. © The Institution of Engineering and Technology 2020.Item Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.Item A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system(Elsevier B.V., 2023) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation. © 2023 Elsevier B.V.Item Analytical modelling of ultra-small group delay variation of ultra-broadband RF power amplifier using NSGA-II algorithm(John Wiley and Sons Ltd, 2024) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This paper proposes a ± 9.4 ps ultra-small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter-stage and power stage topologies. The non-dominated sorting genetic algorithm (NSGA-II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero-pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2. © 2023 John Wiley & Sons Ltd.