Faculty Publications

Now showing 1 - 3 of 3

An Integrated Approach of CNT Front-end Amplifier towards Spikes Monitoring for Neuro-prosthetic Diagnosis
(SpringerOpen, 2018) Kumar, S.; Kim, B.-S.; Song, H.
The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to 80 ?V while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of 2 ?W under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves 60 G? of input impedance and input referred noise of 8.5 nv/Hzover the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists. © 2018, The Korean BioChip Society and Springer-Verlag GmbH Germany, part of Springer Nature.
High-Performance Graphene FET Integrated Front-End Amplifier Using Pseudo-resistor Technique for Neuro-prosthetic Diagnosis
(SpringerOpen, 2022) Naik, J.D.; Gorre, P.; Akuri, N.G.; Kumar, S.; Al-Shidaifat, A.D.; Song, H.
A complex analysis of spike monitoring in neuro-prosthetic diagnosis demands a high-speed sub-nanoscale transistors with an advanced device technologies. This work reports the high performance of Graphene field-effect transistor (GFET) based front-end amplifier (FEA) design for the neuro-prosthetic application. The 9 nm Graphene FET device is optimized by characterization of transconductance and drain current towards high sensitivity and small factor. The proposed GFET-based FEA with pseudo-resistor technique demonstrates very high-input impedance in Tera-ohms that nullify the input leakage current. Here, gain-bandwidth product and noise optimization of GFET FEA enhances the overall gain with negligible noise. The proposed design operates at low voltage, further reduces the power consumption, and achieves less chip area in sub-nano size so it could be more suitable for implantable devices. The GFET-based FEA architecture achieves an action potential spike of 1.4 µV while the local field potentials spike of 1.8 mV. The proposed architecture is implemented in Advanced Design System using the design kit of the GFET process. Power consumption of 3.14 µW is observed with a supply voltage of 0.9 V. The simulated and experimental results of the proposed design achieve an input impedance of 2 TΩ with excellent noise performance over a wideband of 13.85 MHz. The proposed work demonstrates better neural activity sensing when compared to the state-of-the-artwork, which could be highly beneficial for future neuroscientists. © 2022, The Korean BioChip Society.
A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems
(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.
In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023

Faculty Publications

Browse

Filters

Settings

Sort By

Results per page

Search Results