Faculty Publications
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Publications by NITK Faculty
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Item An Integrated Approach of CNT Front-end Amplifier towards Spikes Monitoring for Neuro-prosthetic Diagnosis(SpringerOpen, 2018) Kumar, S.; Kim, B.-S.; Song, H.The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to 80 ?V while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of 2 ?W under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves 60 G? of input impedance and input referred noise of 8.5 nv/Hzover the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists. © 2018, The Korean BioChip Society and Springer-Verlag GmbH Germany, part of Springer Nature.Item Reconfigurable Wide Bandwidth Using Novel Extraction Technique of Slotted Monopole Antenna with RF CNT Network(Springer New York LLC barbara.b.bertram@gsk.com, 2019) Kumar, S.; Song, H.; Kanuajia, B.K.This work first moment focuses on the concept of reconfigurable wide bandwidth using novel extraction technique of slotted monopole antenna with RF carbon nanotube (CNT) network. The entire approach is folded into four different designs. The first design proposes a monopole antenna where asymmetric flower type corners and mushroom shape encloses by T-slot is cut on the patch. This new shaped antenna covers wide impedance bandwidth of about 14.5 GHz within range from 21.5 to 36 GHz. The proposed antenna observed that lower bands are excited with new resonating modes by inserting T-slot upon mushroom shape while higher bands are effected due to asymmetric flower type corners on the patch. A wide range of gain from 16.3 to 20.5 dB with maximum axial ratio bandwidth of 2.8% is also succeed. Measured and simulation results for proposed antenna shows good agreement with each other. In second design, a novel extraction technique is used for equivalent model of slotted monopole antenna which shows promising agreement with the original geometry. Thirdly, introduces RF CNT equivalent model which demonstrates its ability to resonant at wideband within range of 12.4–25.1 GHz with 68% of fractional impedance bandwidth. Finally, RF equivalent model of slotted monopole antenna is integrated with CNT for the proper operation. The fabrication of integration network scenario proves notability of reconfiguration in aspect of wide bandwidth with the compactness. A frequency switchable notability dominant some excited additional resonant modes using proper impedance matching between proposed antenna and RF CNT. This proposed work is fascinating to our integration network which fully covered K-band and almost for Ka-band application. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Item A compact broadband GFET based rectenna for RF energy harvesting applications(Springer, 2020) Singh, N.; Kumar, S.; Kumar Kanaujia, B.K.; Beg, M.T.; Mainuddin, M.; Kumar, S.In this paper, a compact GFET-based rectifier integrated with a monopole antenna is proposed for wireless energy harvesting applications. The GFET increases impedance bandwidth of the rectifying circuit, thus covering a range of 22.5–27.5 GHz. The sensing antenna is a triangular monopole with truncated corners for realizing circular polarization at the frequencies 24.25 GHz and 27 GHz. By the help of ?/4 transformer, the sensing antenna is matched with the proposed GFET rectifier. The RF-DC conversion efficiency realized is 80% at 5 dBm for the load of 5 K?, and the output DC voltage observed is 6.8 V. The modified ground plane triangular monopole antenna shows a peak gain of 7.8 dBi. The designed rectenna prototype is fabricated and found simulated and measured results are in good agreement. © 2020, Springer-Verlag GmbH Germany, part of Springer Nature.Item A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.Item High-Performance Graphene FET Integrated Front-End Amplifier Using Pseudo-resistor Technique for Neuro-prosthetic Diagnosis(SpringerOpen, 2022) Naik, J.D.; Gorre, P.; Akuri, N.G.; Kumar, S.; Al-Shidaifat, A.D.; Song, H.A complex analysis of spike monitoring in neuro-prosthetic diagnosis demands a high-speed sub-nanoscale transistors with an advanced device technologies. This work reports the high performance of Graphene field-effect transistor (GFET) based front-end amplifier (FEA) design for the neuro-prosthetic application. The 9 nm Graphene FET device is optimized by characterization of transconductance and drain current towards high sensitivity and small factor. The proposed GFET-based FEA with pseudo-resistor technique demonstrates very high-input impedance in Tera-ohms that nullify the input leakage current. Here, gain-bandwidth product and noise optimization of GFET FEA enhances the overall gain with negligible noise. The proposed design operates at low voltage, further reduces the power consumption, and achieves less chip area in sub-nano size so it could be more suitable for implantable devices. The GFET-based FEA architecture achieves an action potential spike of 1.4 µV while the local field potentials spike of 1.8 mV. The proposed architecture is implemented in Advanced Design System using the design kit of the GFET process. Power consumption of 3.14 µW is observed with a supply voltage of 0.9 V. The simulated and experimental results of the proposed design achieve an input impedance of 2 TΩ with excellent noise performance over a wideband of 13.85 MHz. The proposed work demonstrates better neural activity sensing when compared to the state-of-the-artwork, which could be highly beneficial for future neuroscientists. © 2022, The Korean BioChip Society.Item A wideband, 25/40dBm high I/O power GaN HEMT ultra-low noise amplifier using even-odd mode techniques(Elsevier Ltd, 2022) Gupta, M.P.; Gorre, P.; Kumar, S.; Nulu, V.This paper presents a performance analysis of the low noise amplifier (LNA) for the first time using even-odd mode matching techniques in Gallium Nitride (GaN) HEMT Technology for marine communication. The proposed GaN LNA circuit consists of broadband stage I, main amplifier, and inverted broadband stage II, which provides a high input/output power, and ultra-low noise over wide bandwidth ranging from 0.5 GHz to 2.7 GHz with fractional impedance bandwidth of 138%. Broadband Stage I and Inverted broadband stage II are employed to provide input/output impedance matching transformation. The proposed LNA circuit with the incorporation of input/output broadband stages relax a 50Ω matching constraints and achieved high input and output power with good stability. The GaN HEMT LNA is analyzed and simulated using the RF simulator (ADS tool). The proposed GaN HEMT LNA is fabricated on RT Duroid substrate using Microwave Integrated Circuit (MIC) technology. The proposed LNA achieves a measured gain of 16 dB, while the simulated one is 17 dB with good insertion loss. An ultra-low noise figure of 0.6 dB flat is achieved over a wide bandwidth. In addition, the high output power is achieved 40dBm while input power is 25dBm which could overcome weak signal strength received by RF receiver for marine communication. A stability factor greater than one is achieved over a broad band ranging from 0.5 GHz to 2.7 GHz. The fabricated GaN HEMT LNA circuit has consumed power of 120 mW under a supply of 28 V. The area of the fabricated RF GaN HEMT LNA is 32 × 26 mm2. © 2022 Elsevier LtdItem A 2.71-pA/√Hz ultra-low noise, 70-dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth(John Wiley and Sons Ltd, 2023) Gorre, P.; Vignesh, R.; Kumar, S.; Song, H.; Roy, G.M.Recent advancements in the area of telemedicine have focused on remote patient monitoring services as a new frontier in medical applications. The present work reports a 65-nm complementary metal–oxide–semiconductor (CMOS)-based transimpedance amplifier (TIA) in an optical radar system for non-contact patient monitoring. A T-shaped microstrip line (MSL) integrated with variable gain common source TIA using MSL peaking technique and off-chip post-amplification integration is a newly proposed architecture to achieve a ultra-low noise, high dynamic range (DR) and high figure of merit over broadband than a traditional TIAs. First, the integrated T-shaped MSL develops an additional resonant frequency that resonates with a photodiode capacitance improving the bandwidth performance at higher Q values. Second, the shunt MSL peaking technique that introduces an additional conjugate pole-pair that cancels the effect of input capacitance helps to further improve the bandwidth of the TIA. Finally, an active feedback concept achieves a wide linear dynamic range enabling high TIA detectability. The proposed TIA realizes an impedance bandwidth of 770 MHz ranging from 7.12 to 7.89 GHz with a transimpedance gain of 105.1 dBΩ and ultra-low input-referred noise (IRN) density of 2.71 pA/√Hz. A high linear DR of 70 dB is achieved by employing a variable gain control scheme with a low group delay variation of 0.81 ns. The proposed work demonstrates a 1-Gb/s data rate while a bit-error rate less than 10−12 is achieved. The TIA consumes a power of 0.82 mW under the supply voltage of 1.2 V. © 2022 John Wiley & Sons Ltd.Item A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband(Elsevier GmbH, 2024) Gupta, M.P.; Kumar, S.; Naik Jatoth, D.; Gorre, P.; Song, H.This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs. © 2024 Elsevier GmbHItem An Ultra-low Noise, Highly Compact Implantable 28 nm CMOS Neural Recording Amplifier(Institute of Electronics Engineers of Korea, 2024) Akuri, N.G.; Naik, D.N.; Kumar, S.; Song, H.; Kar, A.An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 fV/√Hz at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 µW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems. © 2024, Institute of Electronics Engineers of Korea. All rights reserved.