Faculty Publications
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Item A high efficiency on-chip reconfigurable Doherty power amplifier for LTE communication cells(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2018) Kumar, R.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.In this paper, a high efficiency on-chip reconfigurable Doherty power amplifier (DPA) with proposed topology is proposed for LTE or 4G communication cells. The proposed DPA consists of input driver topology, hybrid coupler, asymmetric amplifiers, and 1:1 balun filtered network. The proposed input driver circuit provides wide amplified signal operation within range of 2.3GHz to 6GHz with flat gain of 33 dB. The amplified signal is unsteadily divided into two paths toward the carrier and the power amplifier by 900 hybrid couplers and demonstrates 27.6 dB and 28.3 dB of gain along with 83.2% and 84.5% of power added efficiency at average output power of 40 dBm. The high efficiency and almost flatness in gain stability of proposed DPA providing better solution in order to overcome the interference and the broadband issues for LTE communication cells. The balun-filtered network is employed for combined the two outputs of carrier and peak amplifiers that provides more uniform desired band of operation in the frequency responses. The proposed DPA circuit are implemented and optimized by using advanced design RF simulator platform. The fabricated chip is made by using 0.13 ?m GaN HEMT on Si-Nitride monolithic microwave integrated circuit die process. The fabricated chip of DPA provides 85% of PAE with 28 dB gain which are made close agreement with simulation results. The size of chip is 2.8*1.2mm2 which occupies less die area as compared to existing DPAs. © 2018 Wiley Periodicals, Inc.Item An integrated cascode DE power amplifier for RF calibration system towards measurement of bio-sensor applications(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2019) Kumar, R.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.The integrated cascode DE power amplifier for RF calibration system toward measurement of bio-sensor applications is presented in this paper. The proposed architecture includes cascode class-D and class-E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio-sensor application. The inductive ?-shape matching network drives RF input to class-D stage and provides wide bandwidth of operation. While class-E stage with T-shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of ?50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio-sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class-E consuming area of 38% and class-D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V. © 2018 Wiley Periodicals, Inc.Item Performance of cascode Class-EF?1 PA with built-in techniques for UWB radar toward monitoring of patient actions(Institution of Engineering and Technology kvukmirovic@theiet.org, 2020) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This work proposes a performance of the cascode Class-EF?1 power amplifier (PA) for UWB radar transmitter. The cascode Class-E PA with built-in techniques overcomes the traditional mismatch and provides good performance of PA. Incurs the resonance and switching effect is observed in cascode Class-E PA that compensates for the parasitic effects and provides a wide-impedance range. While design-II includes negative capacitance and inverse Class-F, which achieves a redundant performance of wide bandwidth and power-added efficiency (PAE). Design-II achieves the redundant performance compared with design-I. Both design-I and design-II are implemented and analysed through simulation and experimental results using RF 65 nm Samsung Magnachip Hynix CMOS process. Design-I achieves a wide-impedance bandwidth ranging from 3 to 11.7 GHz with drain efficiency (DE) and maximum PAE of 80 and 73% at the output power of 26.4 dBm. The global efficiency (GE) and error vector magnitude (EVM) of 70 and 5.2% are also achieving for design-I. The redundant performance in design-II achieves wide bandwidth with operating frequency range of 2-13 GHz with maximum DE and PAE of 85 and 76%. For design-II, GE and EVM are investigated as 68 and 4.9% that could validate the accuracy and robustness of the UWB radar. © The Institution of Engineering and Technology 2019Item Improving the Cu2ZnSn(S,Se)4-Based Photovoltaic Conversion Efficiency by Back-Contact Modification(Institute of Electrical and Electronics Engineers Inc., 2021) Sengar, B.S.; Garg, V.; Siddharth, G.; Kumar, A.; Pandey, S.K.; Dubey, M.; Atuchin, V.V.; Kumar, S.; Mukherjee, S.Back-contact modification using a 10-nm ZnS layer in CZTSSe-based solar cell can play a crucial role in improving photovoltaic conversion efficiency. An ultrathin layer of ZnS is deposited over Mo-coated soda lime glass substrate before depositing CZTSSe using sputtering. The crystal structure of deposited CZTSSe thin films over ZnS is recognized as (112)-oriented, polycrystalline in nature, and free from the presence of any secondary phases such as Cu2(S,Se) or Zn(S,Se). The bandgap of CZTSSe thin films deposited over ultrathin ZnS is observed to increase from 1.49 (deposited over Mo directly) to 1.58 eV at room temperature, as determined by spectroscopic ellipsometry. In addition, numerical simulation has been performed using SCAPS software. The impact of ZnS layer has been simulated by using the defects in the absorber and at the interface of ZnS/CZTSSe. The simulated results have been validated with experimentally fabricated CZTSSe device. Simulated device with ZnS intermediate layer is observed to give rise to a photovoltaic conversion efficiency of 15.2%. © 1963-2012 IEEE.Item A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.Item A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system(Elsevier B.V., 2023) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation. © 2023 Elsevier B.V.Item Analytical modelling of ultra-small group delay variation of ultra-broadband RF power amplifier using NSGA-II algorithm(John Wiley and Sons Ltd, 2024) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This paper proposes a ± 9.4 ps ultra-small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter-stage and power stage topologies. The non-dominated sorting genetic algorithm (NSGA-II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero-pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2. © 2023 John Wiley & Sons Ltd.Item A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband(Elsevier GmbH, 2024) Gupta, M.P.; Kumar, S.; Naik Jatoth, D.; Gorre, P.; Song, H.This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs. © 2024 Elsevier GmbH