Faculty Publications

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Author: search.filters.author.Jeeru, D.R.

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    Implementation of Enhanced Parallel port interface for Frequency analysis in a configurable Ring Oscillator PUF circuits on Xilinx Spartan 3E architecture
    (Institute of Electrical and Electronics Engineers Inc., 2019) Jeeru, D.R.; Vittal, K.P.; Anikethan, H.V.U.; Kumar, A.S.
    Hardware security has evolved from physical one-way functions to Physically Unclonable Functions (PUFs). A PUF produces a response for a given challenge by performing a functional operation. This paper demonstrates the Configurable Ring Oscillator (CRO) based PUF circuit with frequency meter. Frequencies are read through Enhanced Parallel Port (EPP) interface to enable efficient communication between the host and the Field Programmable Gate Array (FPGA) device. As a part of the work, 128 CROs are implemented on 128 Configurable Logic Blocks (CLBs) of the Spartan 3E FPGA device and frequencies are measured for every configuration of the CRO to generate the Challenge Response Pair (CRP) for each device. This experimental setup is carried out on 4 different FPGA devices and specific methodologies are used to generate responses which are consistent with time for every reading analyzed and different for different FPGA devices. The process involves selecting the optimum unit time pulse window to measure the frequencies of CROs and optimum number of CROs grouped as hard macro to enhance inter and intra Hamming Distance (HD) consequently improving uniqueness, reliability and uniformity metrics. © 2019 IEEE.
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    Design and modelling an attack on multiplexer based physical unclonable function
    (Seventh Sense Research Group, 2020) Venkata, A.M.; Jeeru, D.R.; Vittal, K.P.
    This paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1). © 2020 Seventh Sense Research Group. All rights reserved.