Faculty Publications
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Item Performance Evaluation in 2D NoCs Using ANN(Springer Science and Business Media Deutschland GmbH, 2022) Kale, P.; Hazarika, P.; Jain, S.; Bhowmik, B.A network-on-chip (NoC) performance is traditionally evaluated using a cycle-accurate simulator. However, when the NoC size increases, the time required for providing the simulation results rises significantly. Therefore, such an issue must be overcome with an alternate approach. This paper proposes an artificial neural network (ANN)-based framework to predict the performance parameters for NoCs. The proposed framework is learned with the training dataset supplied by the BookSim simulator. Rigorous experiments are performed to measure multiple performance metrics at varying experimental setups. The results show that network latency is in the range of 31.74–80.70 cycles. Further, the switch power consumption is in the range of 0.05–12.41 μ W. Above all, the proposed performance evaluation scheme achieves the speedup of 277–2304 × with an accuracy of up to 93%. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.Item AI Technology for NoC Performance Evaluation(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Hazarika, P.; Kale, P.; Jain, S.An on-chip network has become a powerful platform for solving complex and large-scale computation problems in the present decade. However, the performance of bus-based architectures, including an increasing number of IP cores in systems-on-chip (SoCs), does not meet the requirements of lower latencies and higher bandwidth for many applications. A network-on-chip (NoC) has become a prevalent solution to overcome the limitations. Performance analysis of NoC's is essential for its architectural design. NoC simulators traditionally investigate performance despite they are slow with varying architectural sizes. This work proposes a machine learning-based framework that evaluates NoC performance quickly. The proposed framework uses the linear regression method to predict different performance metrics by learning the trained dataset speedily and accurately. Varying architectural parameters conduct thorough experiments on a set of mesh NoCs. The experiments' highlights include the network latency, hop count, maximum switch, and channel power consumption as 30-80 cycles, 2-11, $25\mu \text{W}$ , and $240\mu \text{W}$ , respectively. Further, the proposed framework achieves accuracy up to 94% and speedup of up to $2228\times $. © 2004-2012 IEEE.