Faculty Publications
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Item Undeniable Signature Scheme: A Survey(Institute of Electrical and Electronics Engineers Inc., 2020) Kale, P.; Hazarika, P.; Chandavarkar, B.R.Nowadays, almost all business organizations, committees use the internet to do transactions and confidential information exchange. So it is crucial to make these transactions secure and reliable. A system to be confident and trustworthy needs a function of cryptography, and also it must manage the keys of cryptography. The digital signature, which is universally verifiable, is a solution when there are disputes between the sender and receiver. Later the undeniable signature scheme was introduced as a modern technique to verify the validity of a message sent by the sender. The undeniable signature scheme has its properties to protect the interests of the sender and receiver. An authenticated verifier only can check the signature with the approval of the signer. In this paper, we have discussed various undeniable signature schemes-key generation, signature verification, and disavowal protocol. This paper compares different schemes of the undeniable signature on the various notations of security. © 2020 IEEE.Item Performance Evaluation in 2D NoCs Using ANN(Springer Science and Business Media Deutschland GmbH, 2022) Kale, P.; Hazarika, P.; Jain, S.; Bhowmik, B.A network-on-chip (NoC) performance is traditionally evaluated using a cycle-accurate simulator. However, when the NoC size increases, the time required for providing the simulation results rises significantly. Therefore, such an issue must be overcome with an alternate approach. This paper proposes an artificial neural network (ANN)-based framework to predict the performance parameters for NoCs. The proposed framework is learned with the training dataset supplied by the BookSim simulator. Rigorous experiments are performed to measure multiple performance metrics at varying experimental setups. The results show that network latency is in the range of 31.74–80.70 cycles. Further, the switch power consumption is in the range of 0.05–12.41 μ W. Above all, the proposed performance evaluation scheme achieves the speedup of 277–2304 × with an accuracy of up to 93%. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.Item LR-Based Performance Evaluation of MoCs(Institute of Electrical and Electronics Engineers Inc., 2024) Hazarika, P.; Bhowmik, B.In the recent decade, on-chip communication net-works have developed into a potent platform for tackling chal-lenging and significant computation issues. However, many applications cannot achieve high-performance communication needs due to the seamless integration of computing cores in systems-on-chip (SoCs). Subsequently, a network-on-chip (NoC) has emerged as a prominent on-chip communication infrastructure in SoCs. Performance analysis of NoC's is essential for its architectural design and is traditionally evaluated employing a simulator. How-ever, simulation-based performance evaluation is relatively slow and may take a long time with varying architectural NoC sizes. This paper presents an AI-based approach for investigating mesh-based NoC (MoC) performance over the traditional simulation-based performance evaluation. The proposed framework targets to reach two objectives- quickly and accurately evaluation of various NoC performance metrics. Simulations are performed at varying architectural setups on a set of mesh NoCs to generate the training dataset for the proposed framework. Consequently, the framework satisfactorily predicts different performance metrics. For example, network and packet latency; hop count; switch, channel, and total power consumption; and total area are in the range of 58.14-88.49 and 58.69-106.97 cycles; 6.231-6.257; 1.44-13.02, 13.73-129.06, and 25.26- 177.44 μ W; and 1.35874 μ m2, respectively while the proposed framework is applied on the 9 x 9 mesh NoC. The metrics are with 94% accuracy and predicted at very significantly less time. The LR model saves 99.45 % evaluation time resulting in the speedup of 260 x than a simulation - based method. © 2024 IEEE.Item AI Technology for NoC Performance Evaluation(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Hazarika, P.; Kale, P.; Jain, S.An on-chip network has become a powerful platform for solving complex and large-scale computation problems in the present decade. However, the performance of bus-based architectures, including an increasing number of IP cores in systems-on-chip (SoCs), does not meet the requirements of lower latencies and higher bandwidth for many applications. A network-on-chip (NoC) has become a prevalent solution to overcome the limitations. Performance analysis of NoC's is essential for its architectural design. NoC simulators traditionally investigate performance despite they are slow with varying architectural sizes. This work proposes a machine learning-based framework that evaluates NoC performance quickly. The proposed framework uses the linear regression method to predict different performance metrics by learning the trained dataset speedily and accurately. Varying architectural parameters conduct thorough experiments on a set of mesh NoCs. The experiments' highlights include the network latency, hop count, maximum switch, and channel power consumption as 30-80 cycles, 2-11, $25\mu \text{W}$ , and $240\mu \text{W}$ , respectively. Further, the proposed framework achieves accuracy up to 94% and speedup of up to $2228\times $. © 2004-2012 IEEE.