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Item Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures(Institute of Electrical and Electronics Engineers Inc., 2018) Pasupulety, U.; Halavar, B.; Talawar, B.Through-Silicon Vias(TSVs) are a type of on-chip interconnect used for communication between multiple layers of circuit elements in a 3D IC. Multiple TSVs form a vertical link connecting inter-layer elements in 3D Network-on-Chip(NoC) architectures. Microarchitectural parameters such as length, width, pitch, and operating frequency influence the total power consumed and heat dissipated by TSVs. Effective extraction of the heat between layers is a significant challenge in 3D NoCs. Modelling the power of the TSVs and the thermal profile of 3D NoCs accurately enable designers perform trade-off studies during the design phase. In this work, we evaluate the thermal behaviour of 2 layer 3D Mesh and CMesh NoC architectures. We extended HotSpot to provide support for the inclusion of a router-TSV circuit element as a part of the 3D NoC floorplan. For the 3D Mesh, the thermal behaviour was analyzed for the naive arrangement as well as a proposed thermally aware design of the router-TSV element. Additionally, the thermal effect of multiple cores sharing a single router-TSV in a CMesh architecture was investigated. Our experiments show that the average of the maximum temperatures of all the routers in the 4x8x2 thermal-aware 3D Mesh is lowered by 3% compared to the naive 3D Mesh design. Also, the average of the maximum temperatures of all the routers in a 3D CMesh is 7% more than the naive 3D Mesh and 9% more than the thermally aware 3D Mesh design. © 2018 IEEE.Item Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)(Institute of Electrical and Electronics Engineers Inc., 2018) Pasupulety, U.; Halavar, B.; Talawar, B.A Through Silicon Via(TSV) interconnects vertically stacked layers of circuit elements in a 3D IC. This leads to reduced distance and increased communication bandwidth between any two circuit elements located on different layers of the chip compared to 2D NoCs. TSVs have different physical characteristics and associated latency and power consumption compared to horizontal chip interconnects. The need of the hour is to accurately estimate the power consumption and latency of TSVs separately from horizontal interconnects through simulation. Accurate power and latency models of TSVs enable architects and researchers to arrive at the optimal design space by performing quick trade-off studies. We propose an extension to the BookSim simulator that considers TSVs as a separate type of on-chip interconnect. The associated latency and dynamic power consumption is calculated based on delay and power models involving various physical parameters of the TSV. Upon applying these models in a 3D 4times 4times 4 mesh topology simulation, it is observed that the total average link power consumed is lower than a 2D mesh by 13% when the vertical links(containing TSVs) are treated separately from the horizontal links. Additionally, the average network latency in the 3D mesh topology is roughly 60-82% lower than the 2D case. © 2018 IEEE.