Faculty Publications
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Item A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding(Elsevier B.V., 2020) Girija Sravani, K.; Rao, R.This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines. © 2019 Elsevier B.V.Item Novel Asynchronous Pipeline Architectures for High-Throughput Applications(Springer, 2020) Girija Sravani, K.; Rao, R.This paper introduces two novel high-throughput asynchronous pipeline methods, suitable for gate-level pipelined systems. The proposed methods, named as early acknowledged hybrid (EA-Hybrid) and high-capacity hybrid pipeline with post-detection (PD-Hybrid), use hybrid data paths that can combine the robustness of dual-rail encoding and simplicity of single-rail encoding schemes. The domino logic style has been adopted for constructing the logic gates in each pipeline stage, as it can provide the latch-less feature. The control path of EA-Hybrid is built based on high-speed early acknowledgment protocol, whereas in PD-Hybrid, it is built based on simple and robust 4-phase protocol. Further, both the proposed pipeline styles allow their logic gates into a special state called the isolate phase in addition to precharge and evaluation phases. The isolate phase leads to improvement in pipeline throughput as well as storage capacity. An 8x8 array multiplier has been designed using the proposed pipeline styles and simulated in three different technologies using UMC libraries. In 180 nm technology, the proposed EA-Hybrid method has achieved 40.25% higher throughput and the pipeline style PD-Hybrid has achieved 18.05% higher throughput than the APCDP. © 2020, King Fahd University of Petroleum & Minerals.Item Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Girija Sravani, K.; Rao, R.This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.