Faculty Publications
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Publications by NITK Faculty
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Item High throughput and high capacity asynchronous pipeline using hybrid logic(Institute of Electrical and Electronics Engineers Inc., 2017) Girija Sravani, K.; Rao, R.This paper proposes a novel high throughput and high capacity asynchronous pipeline architecture, named High capacity Hybrid logic pipeline. The proposed pipeline architecture is intended for the data paths that use domino logic. This pipeline structure, combines the merits of hybrid logic encoding scheme(robustness and simplicity) and High capacity single-rail protocol (high throughput and full buffering capacity). The validity of the proposed pipeline structure has been tested by simulating a 4-bit, 10-stage FIFO in 180 nm technology. The FIFO has exhibited a throughput of 2.23 giga-items/s and this number is 23.2% higher than one of the best existing pipeline (High capacity single-rail). © 2017 IEEE.Item DDCVS Logic for Asynchronous Gate-Level Pipelined Circuits(Springer Science and Business Media Deutschland GmbH, 2021) Girija Sravani, K.; Rao, R.This paper proposes a new way of realizing the data paths for asynchronous domino logic gate-level pipeline styles. This novel approach improves the speed of the pipelines by preserving the latch-less feature of domino pipelines. In this work, the data paths of three asynchronous 16-bit adders based on APCDP, LP2/2, and HC-Hybrid pipelines are constructed using dual-rail domino cascode voltage switch (DDCVS) logic and simulated using cadence toolset in 90 nm technology. The adders based on DDCVS logic have exhibited higher performance and lower energy-delay square product compared to the adders based on domino logic. © 2021, Springer Nature Singapore Pte Ltd.Item A 280?W high gain inductively degenerated LNA for medical radio communication(Serials Publications serialspublications@vsnl.net, 2016) Vasudeva Reddy, K.; Girija Sravani, K.; Prashantha Kumar, H.An ultra-low power, high gain inductively degenerated common source (IDCS) LNA for medical radio (MedRadio) communications in the frequency band of 401-406 MHz is implemented using 0.18-?m technology. An upsurge LNA is designed for biomedical applications with an emphasis on the covenant between gain, noise and power consumption. The IDCS LNA operates in subthreshold region which extremely reduces the power consumption and relaxes the voltage headroom without screwing the LNA performance. The relaxed voltage headroom concedes current-reuse technique to implement single to differential (SD) LNA or to stack mixer on top of LNA. The proposed LNA achieves power gain (S21) of 21 dB, S11 & S22 are much less than -10 dB, NF of 2.1 dB and P1dB of -18 dBm while consuming 280 ?A current from a 1-V supply voltage. The overall pre and post layout simulations of proposed LNA shows acceptable agreement with theoretical predictions. The layout occupying 0.587 mm2. The gain enhancement and reduction in power has been optimized compared with previous works implies that LNA obtains the highest figure of merit. © 2016 International Science Press.Item Low power ultra wide-band balun LNA using noise cancellation and current-reuse techniques(Elsevier Ltd, 2017) Vasudeva Reddy, K.; Girija Sravani, K.; Prashantha Kumar, P.A low power, single to differential (balun) low noise amplifier (LNA) using noise cancellation and current re-use techniques is presented for ultra wide-band applications. An upsurge balun LNA is designed using UMC 0.18-?m RF CMOS technology with an emphasis on the covenant between gain, bandwidth and power dissipation. The proposed balun exerts a differential stage on top of common gate-common source (CG-CS) stage. A CG-CS stage exploits amalgamation of CG stage (for wide-band impedance matching) and CS to curtail gain and phase imbalance, while simultaneously negating the noise and distortion of input matching transistor. The escalation of bandwidth has been accomplished using staggered tuning on CG-CS and differential stages. The stacked differential amplifier does cancellation of self noise as well as supply noise. The proposed UWB balun LNA achieves 14 dB voltage gain with agreeable input reverse isolation (S11) of <-8dB over the frequency range of 3.19–8.8 GHz. The minimum noise figure of 3.9 dB and P1dB of ?10.5 dBm while exhausting 3.8 mW from 1.2 V supply. The superlative performance of balun LNA is accomplished between 3.19 and 8.8 GHz with gain and phase errors below 0.2 dB and 0.40 respectively. The layout occupying 0.77 mm2 area. The overall pre and post layout simulations of proposed LNA shows admissible agreement with theoretical predictions. © 2017 Elsevier LtdItem A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding(Elsevier B.V., 2020) Girija Sravani, K.; Rao, R.This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines. © 2019 Elsevier B.V.Item Novel Asynchronous Pipeline Architectures for High-Throughput Applications(Springer, 2020) Girija Sravani, K.; Rao, R.This paper introduces two novel high-throughput asynchronous pipeline methods, suitable for gate-level pipelined systems. The proposed methods, named as early acknowledged hybrid (EA-Hybrid) and high-capacity hybrid pipeline with post-detection (PD-Hybrid), use hybrid data paths that can combine the robustness of dual-rail encoding and simplicity of single-rail encoding schemes. The domino logic style has been adopted for constructing the logic gates in each pipeline stage, as it can provide the latch-less feature. The control path of EA-Hybrid is built based on high-speed early acknowledgment protocol, whereas in PD-Hybrid, it is built based on simple and robust 4-phase protocol. Further, both the proposed pipeline styles allow their logic gates into a special state called the isolate phase in addition to precharge and evaluation phases. The isolate phase leads to improvement in pipeline throughput as well as storage capacity. An 8x8 array multiplier has been designed using the proposed pipeline styles and simulated in three different technologies using UMC libraries. In 180 nm technology, the proposed EA-Hybrid method has achieved 40.25% higher throughput and the pipeline style PD-Hybrid has achieved 18.05% higher throughput than the APCDP. © 2020, King Fahd University of Petroleum & Minerals.Item Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Girija Sravani, K.; Rao, R.This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.