Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
4 results
Search Results
Item An integrated cascode DE power amplifier for RF calibration system towards measurement of bio-sensor applications(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2019) Kumar, R.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.The integrated cascode DE power amplifier for RF calibration system toward measurement of bio-sensor applications is presented in this paper. The proposed architecture includes cascode class-D and class-E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio-sensor application. The inductive ?-shape matching network drives RF input to class-D stage and provides wide bandwidth of operation. While class-E stage with T-shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of ?50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio-sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class-E consuming area of 38% and class-D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V. © 2018 Wiley Periodicals, Inc.Item Performance of cascode Class-EF?1 PA with built-in techniques for UWB radar toward monitoring of patient actions(Institution of Engineering and Technology kvukmirovic@theiet.org, 2020) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This work proposes a performance of the cascode Class-EF?1 power amplifier (PA) for UWB radar transmitter. The cascode Class-E PA with built-in techniques overcomes the traditional mismatch and provides good performance of PA. Incurs the resonance and switching effect is observed in cascode Class-E PA that compensates for the parasitic effects and provides a wide-impedance range. While design-II includes negative capacitance and inverse Class-F, which achieves a redundant performance of wide bandwidth and power-added efficiency (PAE). Design-II achieves the redundant performance compared with design-I. Both design-I and design-II are implemented and analysed through simulation and experimental results using RF 65 nm Samsung Magnachip Hynix CMOS process. Design-I achieves a wide-impedance bandwidth ranging from 3 to 11.7 GHz with drain efficiency (DE) and maximum PAE of 80 and 73% at the output power of 26.4 dBm. The global efficiency (GE) and error vector magnitude (EVM) of 70 and 5.2% are also achieving for design-I. The redundant performance in design-II achieves wide bandwidth with operating frequency range of 2-13 GHz with maximum DE and PAE of 85 and 76%. For design-II, GE and EVM are investigated as 68 and 4.9% that could validate the accuracy and robustness of the UWB radar. © The Institution of Engineering and Technology 2019Item Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.