Faculty Publications

Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736

Publications by NITK Faculty

Browse

Filters

2023 - 20242

Settings

Author: search.filters.author.Chennamadhavuni, S.Has files: No

Search Results

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    An Exploration of the Effective Path for Current Conduction in a Triple Gate Junctionless FinFET
    (Institute of Electrical and Electronics Engineers Inc., 2023) Chennamadhavuni, S.; Mathew, S.; Rao, R.
    The goal of this work is to exclusively investigate the effective path for current conduction in the channel of a Triple Gate (TG) Silicon-ON-Insulator (SOI) Junctionless Fin Field Effect Transistor (JLFinFET). It is observed that various structural parameters play a key role in deciding the location of the effective current path both in full depletion mode and partial depletion mode in TG SOI JLFinFET. Considering the present day technology requirements 20 nm was chosen as the gate length. Simulations performed using 3-D TCAD namely ATLAS by Silvaco Inc. reveal that the conducting path from source to drain starts from nearer to the centre of the channel (i.e, at half the fin height and half the fin width) when the transistor switches from the OFF state to the ON state. It is also observed that when the triple gate transistor scales down in size the capacitive coupling between the top gate and side gates is a crucial factor in determining the location of the effective current path. © 2023 IEEE.
  • No Thumbnail Available
    Item
    An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET
    (Elsevier Ltd, 2024) Mathew, S.; Chennamadhavuni, S.; Rao, R.
    In this work, Fourier series-based analytical models for threshold voltage (Vth) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of Vth for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm. © 2024 Elsevier Ltd