Faculty Publications

Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736

Publications by NITK Faculty

Browse

Filters

20192

Settings

Author: search.filters.author.Bonthala, S.Subject: search.filters.subject.Operational Transconductance Amplifier

Search Results

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    Design of High Gain Operational Transconductance Amplifiers in 180 nm CMOS technology
    (Institute of Electrical and Electronics Engineers Inc., 2019) Nayak, A.; Bonthala, S.; Uppoor, Y.; Bhat, M.S.
    This paper presents two architectures of two-stage Operational Transconductance Amplifiers (OTAs). To achieve high gain, folded cascode topology is used. The first architecture uses an external bias which can be controlled independent of the OTA gain and bandwidth, while the second architecture uses a self-bias which reduces the power dissipation at the expense of restricted control over gain and bandwidth tuning. The two topologies are implemented using UMC 180 nm CMOS 1P9M technology. Both the architectures provide higher gain and consume less power in comparison to the previously published results. © 2019 IEEE.
  • No Thumbnail Available
    Item
    Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology
    (Institute of Electrical and Electronics Engineers Inc., 2019) Bonthala, S.; Uppoor, Y.; Nayak, A.; Polineni, S.; Bhat, M.S.
    This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V. © 2019 IEEE.