Faculty Publications
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Item Performance Evaluation in 2D NoCs Using ANN(Springer Science and Business Media Deutschland GmbH, 2022) Kale, P.; Hazarika, P.; Jain, S.; Bhowmik, B.A network-on-chip (NoC) performance is traditionally evaluated using a cycle-accurate simulator. However, when the NoC size increases, the time required for providing the simulation results rises significantly. Therefore, such an issue must be overcome with an alternate approach. This paper proposes an artificial neural network (ANN)-based framework to predict the performance parameters for NoCs. The proposed framework is learned with the training dataset supplied by the BookSim simulator. Rigorous experiments are performed to measure multiple performance metrics at varying experimental setups. The results show that network latency is in the range of 31.74–80.70 cycles. Further, the switch power consumption is in the range of 0.05–12.41 μ W. Above all, the proposed performance evaluation scheme achieves the speedup of 277–2304 × with an accuracy of up to 93%. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.Item Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks(Springer, 2020) Bhowmik, B.The networks-on-chip (NoCs) as the prevalent interconnection infrastructure have been continuously replacing the contemporary chip microprocessors (CMPs) while high performance computing is the dominant consideration. Aggressive technology scaling progressively reduces the feature size of the chips resulting in increasing susceptibility to failures and breakdowns due to open faults on communication channels. The reliability and performance issues are then becoming more critical requirement in both current and future NoC-based CMPs. This paper first presents an on-line, distributed built-in-self-test (BIST) oriented test mechanism that particularly detects open faults on communication channels and identifies faulty wires from the channels in NoCs. Next, a suitable test scheduling scheme is presented in order to reduce the overall test time and related performance overhead due the fault. Such scheduling scheme makes the present test solution scalable with large scale NoC architectures in general. Implementation of the test mechanism takes little hardware area and few clocks to detect the fault in channels. The on-line evaluation of the proposed test solution demonstrates the effect of the channel-open faults on the NoC performance characteristics at large real like synthetic traffic. In comparison to wide range of prior works on 16-bit networks, the present scheme provides many advantages, e.g., it improves hardware area overhead by 35.36–67.73% and saves the test time by 96.43%. packet latency and energy consumption by 5.83–42.79% and 6.24–46.38%, respectively on the networks, the proposed scheme becomes competitive with the existing works. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.Network-on-chip (NoC) has emerged as a scalable on-chip communication platform and, hence, has become more popular. However, as the sole communication medium, a single point of failure raised by any permanent fault can cause the failure of the entire system. Subsequently, the NoC has become a critically exposed unit that must be protected. This article primarily presents a test-time-independent and optimally distributed test scheme named 'Dugdugi' that addresses channel faults, e.g., short in an Octagon and similar NoC architectures to achieve high reliability. The proposed scheme is extended to cover other channel faults, such as stuck-at and transient faults, to give its impression of a comprehensive approach. Experimental results show that the proposed scheme incurs little hardware area and detects all modeled short faults by a few clocks with achieving fault coverage metric up to 100%. Online evaluation reveals the effect of channel-short faults on various network performance metrics. In comparison to prior methodologies, the proposed scheme improves hardware area overhead up to 71.79% and reduces test time over 94.20%. Furthermore, performance overhead, such as packet latency and energy consumption, reduces up to 40.85% and 43.87%, respectively. © 1993-2012 IEEE.Item AI Technology for NoC Performance Evaluation(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Hazarika, P.; Kale, P.; Jain, S.An on-chip network has become a powerful platform for solving complex and large-scale computation problems in the present decade. However, the performance of bus-based architectures, including an increasing number of IP cores in systems-on-chip (SoCs), does not meet the requirements of lower latencies and higher bandwidth for many applications. A network-on-chip (NoC) has become a prevalent solution to overcome the limitations. Performance analysis of NoC's is essential for its architectural design. NoC simulators traditionally investigate performance despite they are slow with varying architectural sizes. This work proposes a machine learning-based framework that evaluates NoC performance quickly. The proposed framework uses the linear regression method to predict different performance metrics by learning the trained dataset speedily and accurately. Varying architectural parameters conduct thorough experiments on a set of mesh NoCs. The experiments' highlights include the network latency, hop count, maximum switch, and channel power consumption as 30-80 cycles, 2-11, $25\mu \text{W}$ , and $240\mu \text{W}$ , respectively. Further, the proposed framework achieves accuracy up to 94% and speedup of up to $2228\times $. © 2004-2012 IEEE.