Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
59 results
Search Results
Item Impact of process variation induced transistor mismatch on sense amplifier performance(2006) Rodrigues, S.; Bhat, M.S.Sense amplifier is a very critical peripheral circuit in memories as its performance strongly affects both memory access time, and overall memory power dissipation. As the device dimensions scale below 100nm, the process variations are increasing and are impacting the circuit design significantly. The circuit yield loss caused by the process and device parameter variation has been more pronounced than before [1]. In this paper, effects of process variation induced transistor mismatch on sense amplifier performance are studied. A comparative study of the effect of mismatch on delay and yield for different sense amplifier configurations at 90nm technology is presented. © 2006 IEEE.Item AutoLibGen: An open source tool for standard cell library characterization at 65nm technology(2008) Rachit, I.K.; Bhat, M.S.In this paper, we present the development of an open source tool, AutoLibGen, for characterising a standard cell library comprising of basic combinational circuits. The cells are initially laid out and the parasitic netlists are extracted. Unlike the traditional method of computing timing and power data using non linear delay and power models we use more accurate Composite Current Source (CCS) based characterization for very deep sub-micron technologies. We tested our tool with a library for 65nm. The library file generated by our tool was successfully compiled by Synopsys Library Compiler and is used to synthesize a Verilog code using Synopsys Design Compiler. ©2008 IEEE.Item Design of CMOS RF receiver front-end for IEEE 802.11b(2008) Konidala, N.; Bhat, M.S.This paper presents the design of a fully integrated receiver front-end for a 2.4GHz RF transceiver. The proposed receiver front end (Low-Noise Amplifier and Mixer) is based on a direct conversion architecture designed in 0.18μm CMOS technology. The chip provides a down conversion gain to the 50 MHz IF of 13.2 dB, SSB Noise Figure (NF) of 7.65 dB and a 3rd-order input intercept point (IIP3) of -14.6dBm consuming 50.6mW at1.8 V. ©2008 IEEE.Item Design of resolution adaptive TIQ flash ADC using AMS 0.35μm technology(2008) Rajashekar, G.; Bhat, M.S.This paper presents a Resolution Adaptive Flash A/D Converter design and its performance. To achieve high speed, the proposed A/D converter utilizes Threshold Inverter Quantization technique replacing conventional analog comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analog nodes in the ADC. The proposed ADC is a true variable resolution ADC, operates at 3-bit, 4-bit, 5-bit and 6-bit precision depending on control inputs. The proposed ADC is designed with AMS 0.35μm CMOS technology and 3.3V power supply voltage and a prototype chip is fabricated. Simulation results and test results are presented. ©2008 IEEE.Item Performance enhancement in high speed on-chip interconnect lines(2010) Soorya Krishna, K.; Bhat, M.S.An interconnect line along with a series inductor can be used as a resonant network for transmitting high frequency data/clock in an integrated circuit. In this paper, the design of an active inductor circuit and its use in a global interconnect line to form a resonant network for reducing interconnect delay and area is described. An active inductor in place of on-chip passive inductor reduces interconnect latency by 38% and area by 300 times at an operating frequency of 2 GHz in 0.18 μm technology. Monte Carlo simulations are carried out to find the range of interconnect delay variations and output voltage fluctuations due to process and mismatch variations in the active inductor circuit. ©2010 IEEE.Item Estimation of interconnect metrics using state space approach(2010) Soorya Krishna, K.; Pramod, M.; Bhat, M.S.In this paper, we propose models for single and coupled on-chip global interconnect lines by distributed RLGC parameters using state space approach. Models for single and coupled lines are validated by comparing with SPICE simulations. Interconnect performance metrics are obtained from the proposed models for 65 nm, 90 nm, 130 nm and 180 nm technology nodes based on PTM values. In case of coupled interconnect lines, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and illustrated by applying our modeling approach to four coupled interconnect lines. ©2010 IEEE.Item Impedance matching for the reduction of via induced signal reflection in on-chip high speed interconnect lines(2010) Krishna K, S.; Bhat, M.S.Advancements in VLSI technology has made it possible to have more than eight metal layers connecting millions of closely placed devices in a single IC chip. Different interconnect layers run across the chip and the necessary connections across the layers are made through vias. The impedance discontinuity at the junction of the via and the interconnect line creates signal reflections and contributes to the loss of the signal. This paper proposes a method for the reduction of via induced signal reflection in multi layer high speed on-chip interconnect structures. At the junction of the interconnect and the via, impedance mismatch is reduced by the inclusion of an appropriate capacitive load. In this paper, we show the reduction in signal reflection upto a frequency of 9 GHz using the proposed model for the dimensions of 65 nm technology node in the case of two interconnect layers connected through a single via. ©2010 IEEE.Item Selective image smoothing and feature enhancement using modified shock filters(2011) Bini, A.A.; Bhat, M.S.Shock filters are widely used for image enhancement and deblurring. These filters make use of nonlinear hyperbolic Partial Differential Equations (PDEs) in order to sharpen the edges. However, in many practical cases images are corrupted by noise and other kind of degradations. Convensional shock filters are not suitable in such cases as they enhance the noise present in the image. Hence, the idea of combining shock filters with diffusion yield good results. In this paper we propose a modified "diffusion coupled shock filter." The proposed method makes use of an 'adaptive diffusion term' which limits the extent of smoothing on important edges making them more sharper. The experimental results demonstrate the efficiency of the proposed method to control diffusion and to make the reconstruction more reliable. © 2011 IEEE.Item An adaptive total variation model with local constraints for denoising partially textured images(2011) Bini, A.A.; Bhat, M.S.; Jidesh, P.Denoising algorithms such as Total Variation model modify smooth areas in images into piecewise constant patches and small scale details and textures present in the original image are not preserved satisfactorily by these processes. In this paper, we present an algorithm based on an adaptive Total Variation norm of the gradient of the image, with a family of local constraints for efficient denoising of natural images. In fact, natural images consist of smooth and textured regions. Staircase effect is reduced in smooth areas by using a modified Total Variation functional. The set of local constraints, one for each pixel in the image are able to preserve most of the fine details and textures in the images. Visual and quantitative results of proposed method are presented and are compared with results of existing methods. © 2011 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE).Item A fourth-order Partial Differential Equation model for multiplicative noise removal in images(IEEE Computer Society, 2013) Bini, A.A.; Bhat, M.S.In coherent imaging, the sensed images are usually corrupted with multiplicative data dependent noise. Unlike additive noise, the presence of multiplicative noise destroys the information content in the original image to a great extent. In this paper, we propose a new fourth-order Partial Differential Equation (PDE) model with a noise adaptive fidelity term for multiplicative Gamma noise removal under the variational Regularization framework. Variational approaches for multiplicative noise removal generally consist of a maximum a posteriori (MAP) based fidelity term and a Total-Variation (TV) regularization term. However, the second-order TV diffusion approximates the observed images with piecewise constant images, leading to the so-called block effect. The proposed model removes the multiplicative noise effectively and approximates observed images with planar ones making the restored images more natural compared to the second-order diffusion models. The proposed method is compared with the recent state-of-the art methods and the effective restoration capability of the filter is demonstrated experimentally. © 2013 IEEE.