Faculty Publications

Now showing 1 - 4 of 4

Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion
(Kluwer Academic Publishers, 2014) Bini, A.A.; Bhat, M.S.
Speckle is a form of multiplicative and locally correlated noise which degrades the signal-to-noise ratio (SNR) and contrast resolution of ultrasound images. This paper presents a new anisotropic level set method for despeckling low SNR, low contrast ultrasound images. The coefficient of variation, a speckle-robust edge detector is embedded in the well known geodesic "snakes" model to smooth the image level sets, while preserving and sharpening edges of a speckled image. The method achieves much better speckle suppression and edge preservation compared to the traditional anisotropic diffusion based despeckling filters. In addition, the performance of the filter is less sensitive to the speckle scale of the image and edge contrast parameter, which makes it more suitable for the detection of low contrast features in an ultrasound image. We validate the method using both synthetic and real ultrasound images and quantify the performance improvement over other state-of-the-art algorithms in terms of speckle noise reduction and edge preservation indices. © 2012 Springer Science+Business Media, LLC.
14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.
In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.
A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications
(John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.
A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.
CCD Sensor Based Cameras for Sustainable Streaming IoT Applications With Compressed Sensing
(Institute of Electrical and Electronics Engineers Inc., 2023) Gambheer, R.; Bhat, M.S.
This paper presents a comprehensive study of compressed sensing (CS) techniques applied to Charge Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS) sensor-based cameras. CS is a powerful technique for reducing the number of measurements required to capture high-quality images while maintaining a high signal-to-noise ratio (SNR). In this study, we propose a novel CS method for CCD and CMOS sensor-based cameras that combines a new sampling scheme with a sparsity-inducing transform and a reconstruction algorithm to achieve high-quality images with fewer measurements. This paper focuses on an efficient CCD image capturing system suitable for embedded IoT applications. Hardware implementation has been done for proof of concept with an onboard Field Programmable Gate Array (FPGA) performing the compression. This hardware module is used over a wireless network to transmit and receive images under different test conditions with both CMOS and CCD sensors. For each use case, Peak Signal to Noise Ratio (PSNR), average power, and memory usage are computed under different ambient lighting conditions from dark to very bright. The results show that, a 640× 480 CCD sensor with compressed sensing with a sparsity of 0.5, provides 13% power saving and 15% memory saving compared to uncompressed sensing in no-light condition, resulting in 25.76 dB PSNR. Whereas, in no light condition, CMOS sensor does not capture any image at all. These results shows that the CCD image capturing system with compressed sensing can be conveniently used for embedded IoT applications. The data recovery from wireless sensor network is done at a central office where computing time and processing power resources are not constrained. The weight of the CCD camera is approximately 100 grams with modular build approach. © 2013 IEEE.

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