Faculty Publications
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Publications by NITK Faculty
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Item A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption(2013) Lad, K.; Bhat, M.S.A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. © 2013 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.Item A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture(IEEE Computer Society help@computer.org, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact switched capacitor integrator (SCI) based successive approximation register (SAR) analog to digital converter (ADC) for data acquisition system is presented. This technique requires an operational transconductor amplifier (OTA), a comparator and four equal sized capacitors of moderate value for fully differential approach and the architecture is resolution independent. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of a switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the SC integrating capacitor. ADC being fully differential nature has wide input range and it is parasitic insensitive to a large extent. As a stand alone data converter it has small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8 V supply, has effective number of bits (ENOB) of 9.5 at Nyquist frequency. The ADC occupies small die area compared to SAR with a binary weighted capacitor array. © 2019 IEEE.