Faculty Publications
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Publications by NITK Faculty
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Item A 1.2V 1.3μW Cascode Current Reuse Based Neural Amplifier with 113 dB Open-Loop Gain(Institute of Electrical and Electronics Engineers Inc., 2023) Korada, S.; Bhat, M.S.One of the major challenges in the acquisition of neural signals is the design of electronic signal acquisition system. Specialized amplifier circuitry is required in the neural recording system to accurately extract information from weak neural signals. High gain, high input impedance amplifiers are part of such systems. This paper presents the design of a high gain modified casocde current reuse open loop amplifier suitable for such applications. The amplifier has a open loop gain of 113 dB, a bandwidth of 10 kHz and unity-gain bandwidth (UGB) of 6.6 MHz. Further, design and simulation of high gain and low power neural amplifier is presented which uses the proposed high gain modified cascode current reuse amplifier with capacitive feedback. The neural amplifier has a closed loop gain of 45.8 dB over 85 Hz - 8.2 kHz and consumes approximately 1.3 μW of power. The design and the simulation is done using the UMC 90nm CMOS process employing 1.2 V power supply. The small signal DC gain, bandwidth and power of the neural amplifier are found to be better than the previously published works. © 2023 IEEE.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier Ltd