Faculty Publications
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Publications by NITK Faculty
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Item Compressed Sensing for Energy and Bandwidth Starved IoT Applications(Institute of Electrical and Electronics Engineers Inc., 2018) Ramachandra, G.; Bhat, M.S.Ensuring security through the use of video surveillance cameras at public places is becoming attractive these days, thanks to the efficient compression, transmission and storage schemes. To up-scale the surveillance mechanism to large sensor networks, it is imperative that the applications become compatible to wireless sensor networks using Internet of Things (IoT) infrastructure. IoT nodes are generally energy and bandwidth-limited owing to their small size and large scale deployment. Therefore, any image/video acquisition application using IoT infrastructure should function within these constraints. Compressed sensing (CS) is one such paradigm that uses simultaneous sensing and compression and provides a technique for efficient image/video acquisition. This paper investigates the use of compressed sensing for image acquisition in IoT based applications that suffer from energy, bandwidth and storage limitations. © 2018 IEEE.Item 14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.Item A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique(Springer Verlag, 2019) Polineni, S.; Bhat, M.S.; Rajan, A.A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology. © 2018, King Fahd University of Petroleum & Minerals.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item Optimized Compressed Sensing for IoT: Advanced Algorithms for Efficient Sparse Signal Reconstruction in Edge Devices(Institute of Electrical and Electronics Engineers Inc., 2024) Gambheer, R.; Bhat, M.S.In the rapidly advancing field of the Internet of Things (IoT), the capability to process data in real-time within edge devices that have limited computational and energy resources remains a significant challenge. Traditional methods of data acquisition and processing often fail to meet these demands, leading to inefficiencies and compromised data integrity. Addressing this critical gap, our paper introduces three innovative compressed sensing algorithms specifically designed for IoT applications: Structured Random Compressed Sampling Matching Pursuit (SRCoSaMP), Sparse Adaptive Reconstruction Scheme (SPARS), and Real Time Sparse IoT (RTSI). These algorithms are specially designed to process data quickly and effectively, despite the limited resources available on edge devices. We delve into the intricate design and mathematical foundations of each algorithm, emphasizing their adaptability, real-time processing capabilities, and energy efficiency. Empirical evaluations demonstrate their superior performance in terms of real-time data processing efficiency, recovery accuracy, and computational resource management. The findings of our research mark a significant step forward in the domain of IoT data processing, offering robust solutions that ensure data integrity with minimal data samples. © 2013 IEEE.