Faculty Publications

Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736

Publications by NITK Faculty

Browse

Author: search.filters.author.Bhat, M.S.Subject: search.filters.subject.Delta Sigma Modulator

Search Results

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    A Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulator
    (Institute of Electrical and Electronics Engineers Inc., 2018) Aparna, T.; Polineni, S.; Bhat, M.S.
    The design and simulation of a low power, high gain three stage operational transconductance amplifier (OTA) is presented. This OTA has a DC gain of 73.5 dB, a unity gain bandwidth (UGB) of 39.8 MHz and a phase margin of 59°. The total power consumed by OTA is 332 μW. The DC gain and the power dissipation parameters of the OTA are found to be better than the previously published results of [1]-[4]. Further, a first order Delta Sigma Modulator (DSM) is designed as a vehicle to test the OTA by integrating it with a comparator and a DAC for a signal bandwidth of 2 kHz with an oversampling ratio (OSR) of 250 for low frequency biomedical applications. All the blocks are designed using UMC 180nm CMOS 1P9M technology, with 1.8 V supply voltage. The simulation results show that the in-band signal to noise and distortion ratio (SNDR) of the DSM is 53 dB, which is equivalent to 8.5 effective number of bits (ENOB). © 2018 IEEE.
  • No Thumbnail Available
    Item
    Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology
    (Institute of Electrical and Electronics Engineers Inc., 2019) Bonthala, S.; Uppoor, Y.; Nayak, A.; Polineni, S.; Bhat, M.S.
    This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V. © 2019 IEEE.