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An Efficient AI-Based Classification of Semiconductor Wafer Defects using an Optimized CNN Model
(Institute of Electrical and Electronics Engineers Inc., 2023) Pandey, C.; Bhat, K.G.
Wafer maps used to display defect patterns in the integrated circuits industry include crucial information that quality engineers may utilize to identify the cause of a defect and increase yield. In this paper, we put forth a framework for accurately and quickly categorizing semiconductor wafer faults utilizing particularly CNN-based models. This paper seeks to provide a scalable, adaptive, and user-friendly implementation of convolutional neural networks for applications classifying semiconductor defects. In categorizing the defects found on semiconductor wafers, the suggested CNN model obtained an accuracy of 90.50% & 92.28% and losses of 0.39 & 0.29 while performing the training and validation, respectively, along with the misclassification rate of 0.0772. The suggested model also learns rapidly on the validation set at a rate of 1e-03 per second. The proposed custom CNN model architecture incorporates only two convolution layers, resulting in a greatly reduced number of parameter weights and biases. Specifically, the number of parameters is only 44000, which makes the model more compact, cost-effective, and robust against random noise. Moreover, this model can function well under low power and processing limits. Â© 2023 IEEE.