Faculty Publications
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Item A novel characterization and performance measurement of memristor devices for synaptic emulators in advanced neuro-computing(MDPI AG indexing@mdpi.com Postfach Basel CH-4005, 2020) Al-Shidaifat, A.; Chakrabartty, S.; Kumar, S.; Acharjee, S.; Song, H.The advanced neuro-computing field requires new memristor devices with great potential as synaptic emulators between pre-and postsynaptic neurons. This paper presents memristor devices with TiO2 Nanoparticles (NPs)/Ag(Silver) and Titanium Dioxide (TiO2) Nanoparticles (NPs)/Au(Gold) electrodes for synaptic emulators in an advanced neurocomputing application. A comparative study between Ag(Silver)-and Au(Gold)-based memristor devices is presented where the Ag electrode provides the improved performance, as compared to the Au electrode. Device characterization is observed by the Scanning Electron Microscope (SEM) image, which displays the grown electrode, while the morphology of nanoparticles (NPs) is verified by Atomic Force Microscopy (AFM). The resistive switching (RS) phenomena observed in Ag/TiO2 and Au/TiO2 shows the sweeping mechanism for low resistance and high resistance states. The resistive switching time of Au/TiO2 NPs and Ag/TiO2 NPs is calculated, while the theoretical validation of the memory window demonstrates memristor behavior as a synaptic emulator. Measurement of the capacitor-voltage curve shows that the memristor with Ag contact is a good candidate for charge storage as compared to Au. The classification of 3 x 3 pixel black/white image is demonstrated by the 3 x 3 cross bar memristor with pre-and post-neuron system. The proposed memristor devices with the Ag electrode demonstrate the adequate performance compared to the Au electrode, and may present noteworthy advantages in the field of neuromorphic computing. © 2019 by the authors. Licensee MDPI, Basel, Switzerland.Item A Conceptual Investigation at the Interface between Wireless Power Devices and CMOS Neuron IC for Retinal Image Acquisition(MDPI, 2020) Al-Shidaifat, A.; Kumar, S.; Chakrabartty, S.; Song, H.In this paper, a conceptual investigation of the interface between wireless power devices and a retina complementary metal oxide semiconductor (CMOS) neuron integrated circuit (IC) have been presented. The proposed investigation consists of three designs: design-I, design-II, and design-III. Design-I involves a slotted loop monopole antenna as per American National Standards Institute (ANSI) guidelines, which achieve an ultra-wide band ranging from 3.1 GHz to 10.6 GHz. The biocompatible antenna is made on silicon-nitride substrate using on-wafer packaging technology and it is used as a receiver device. The performance of antenna provides a wideband, sufficient power to receive, and low losses due to the avoidance of printed circuit board (PCB) fabrication. A CMOS based multi-stack power harvesting circuit achieves the output power ranging from 4 mW to 2.7 W and corresponds from the selected Radio Frequency (RF) bands of loop antenna is exhibited in design-II. The power efficiency of 40% to 82%, with respect to output powers of 4 mW to 2.7 W, is achieved. Design-III includes a CMOS based retina neuron circuit that employs a dynamic feedback technique and support to achieve the number of read-out spikes. At the end of the interface between wireless power devices and a CMOS retina neuron IC, 50 mV read-out spikes are achieved, with varying light intensity, from 0 mW/cm2 to 2 mW/cm2. The proposed design-II and design-III are implemented and fabricated using commercial CMOS 0.065 µm, Samsung process. The antenna and RF power harvesting IC could be placed on a contact lens platform while retina neuron IC can be implanted after ganglions cells inside the eye. The antenna and harvesting IC are physically connected to the retina circuit in the form of light. This conceptual investigation could support medical professionals in achieving an interfacing approach to restore the image visualization. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.Item An artificial bridge circuit approach between two biological neurons using nanoscale topologies towards paralytic disorders(Elsevier Ltd, 2023) Haque, M.N.; Gorre, P.; Naik, D.N.; Kumar, S.; Al-Shidaifat, A.; Song, H.The advent of Nanoscale IC technology towards pulse-based neural systems reactivates the dead nervous about restoring the functionality of paralytic disorders. This work reports in first time a design of a novel CMOS biological neuron system, which replaces a dead neuron between two neurons to restore communication in paralyzed individuals. The work binds into three stages: design of a spiking leaky Integrator and Fire (LIF) neuron with refractory period mechanisms, which achieves a low power consumption of 2.4 μW, in the first stage; an adaptive homeostatic synapse with short and long-term spike plasticity, that reconfigure the spiking neuron networks of multichannel sensor electrodes to record the electric signal from the active cell as second stage; the final stage presents a low-power common source current reuse regulated cascode (CS-CR-RGC) TIA for amplifying the weak synapse current signal, which achieves a high gain of 135.71 dBΩ with an optimized noise performance of 0.19 pA/Hz. The entire work is designed and implemented using a CMOS 65 nm commercial process that occupies a die area of 400 μm × 120 μm. © 2023Item A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023Item Performance Analysis of Novel Graphene Process Low-Noise Amplifier with Multi-stage Stagger-Tuned Approach over D-band(Springer, 2024) Nandini, P.; Naik, D.N.; Gorre, P.; Gupta, M.P.; Kumar, S.; Al-Shidaifat, A.; Song, H.This work reports an ultra-low noise, multi-stage stagger-tuned low-noise amplifier (MS-ST-LNA) over the D-band performance and achieves a best trade-off between noise, bandwidth, and gain parameters. The ultra-low-noise is achieved in three ways: First, the high-gain 3-stage stagger tuned amplifier (STA) realizes a 3X gain compared to the conventional single-stage amplifier, which sets a low floor noise. Second, the stagger-tuned amplifier achieves 1.6 times lower noise than the traditional single-stage amplifier. Finally, the stagger tune realizes a high-order transfer function, which mitigates the high-frequency noise. The full LNA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using a 0.065-?m commercial process, occupying an area of 0.21 mm2. The proposed design achieves an optimum performance: a maximum measured gain of 20.5 dB and a minimum noise figure (NF) of 4.2 dB over 123.7 to 162.5 GHz. The proposed LNA consumes ultra-low power consumption of 21.3 mW under the power supply of 1.2 V. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.