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Author: search.filters.author.Achala, G.Subject: search.filters.subject.NAND flash memory

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    On the Synthesis of Channel Codes for NAND flash devices in Space Application
    (Institute of Electrical and Electronics Engineers Inc., 2024) Achala, G.; Srihari, P.; Shripathi Acharya, U.S.
    NAND flash memory technology is an important component that is vital in enabling data storage and processing capabilities for deep space missions. Thus, it plays an important role in contributing to the success and scientific outcomes of exploration endeavors beyond Earth's orbit. Its non-volatile characteristic guarantees data integrity even when power is unavailable, a critical attribute for extended missions where power resources are constrained. To improve the data integrity in NAND flash devices used in space applications, appropriate channel codes have to be incorporated. In this work, we have synthesized channel codes for two different NAND flash memory architectures used in space applications. The designed codes provide improved bit error rates when compared with the state-of-the-art. By incorporating suitably designed Subfield Subcodes of Reed Solomon (SSRS) codes in flash memory devices, the device is able to return stored data at acceptable bit error rates even when the raw bit error rate is as high as 10-3 © 2024 IEEE.
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    FPGA Implementation of SSRS Codes for NAND Flash Memory Device
    (Institute of Electrical and Electronics Engineers Inc., 2024) Achala, G.; Nandana, S.; Jomy, F.; Girish, M.M.; Shripathi Acharya, U.S.; Srihari, P.; Cenkarmaddi, L.R.
    NAND flash memory is a non-volatile storage device that is extensively used in personal electronic gadgets, digital television, digital cameras, and many consumer/ professional electronics devices. Error control coding techniques have been incorporated to improve the integrity of information stored in these devices. We have synthesized the Subfield Subcodes of Reed Solomon codes (SSRS) for use on Multi-Level cell (MLC), Triple Level Cell (TLC), and Quadruple Level Cell (QLC) NAND flash devices. The primary advantage of these codes is that the codeword symbols can be correctly matched to the number of bits that can be stored in these multilevel cells. Deployment of these codes improves the integrity of information storage and useful life. This paper describes the implementation of the encoder and decoder of SSRS codes synthesized for MLC, TLC, and QLC NAND flash devices. The encoder circuit is designed using addition and multiplication tables derived from elements of synthesized SSRS codes. The Non-binary decoding procedure consists of the syndrome computation, Berlekamp -Massey algorithm, Chein search, and Forney's algorithm. The designed encoder requires 16% resources for MLC, 18% of resources for TLC, and 18% of resources for QLC. This research work has reported the design of very high rate (R ≥ 0.97) codes that can bring about significant improvements to the Undetected Bit Error Rate (UBER) even when the Raw Bit Error rate (RBER) values are significant (> 10-3). © 2013 IEEE.