Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
2 results
Search Results
Item On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories(Institute of Electrical and Electronics Engineers Inc., 2023) Achala, G.; Shripathi Acharya, U.S.; Srihari, P.The revolution in the field of information processing systems has created a huge demand for reliable and enhanced data storage capabilities. This demand is being met by advances in channel coding algorithms along with upward scaling of the capacities of hardware devices. NAND Flash memory is a type of non-volatile memory. Scaling of the size of flash memories from Single Level Cell (SLC) devices to Multilevel cell (MLC) devices has increased the storage capacity. However, these multi-bit per cell architectures are characterized by significantly higher Raw Bit Error Rate (RBER) values when compared with SLC architectures. The requirement of low Undetected Bit Error Rate (UBER) values has motivated us to synthesize powerful channel codes for enhancing the integrity of information Storage in multi-level NAND Flash Memory devices. This paper describes the synthesis of novel Subfield Subcodes of Reed Solomon Codes (SSRS) and Reed-Solomon (RS) codes which are matched to multi-bit per cell architectures. UBER values have been calculated for each of the synthesized codes described in this paper. This allows the determination of the performance and the improvement in data storage integrity brought by using these codes. We have shown that the synthesized SSRS and RS codes can provide very low UBER even when the corresponding RBER values are appreciable. As RS codes permit the detection and correction of a greater number of errors for a given code length, their performance is superior to that of SSRS codes. This improved performance is obtained at the cost of greater complexity of encoding and decoding processes. © 2013 IEEE.Item FPGA Implementation of SSRS Codes for NAND Flash Memory Device(Institute of Electrical and Electronics Engineers Inc., 2024) Achala, G.; Nandana, S.; Jomy, F.; Girish, M.M.; Shripathi Acharya, U.S.; Srihari, P.; Cenkarmaddi, L.R.NAND flash memory is a non-volatile storage device that is extensively used in personal electronic gadgets, digital television, digital cameras, and many consumer/ professional electronics devices. Error control coding techniques have been incorporated to improve the integrity of information stored in these devices. We have synthesized the Subfield Subcodes of Reed Solomon codes (SSRS) for use on Multi-Level cell (MLC), Triple Level Cell (TLC), and Quadruple Level Cell (QLC) NAND flash devices. The primary advantage of these codes is that the codeword symbols can be correctly matched to the number of bits that can be stored in these multilevel cells. Deployment of these codes improves the integrity of information storage and useful life. This paper describes the implementation of the encoder and decoder of SSRS codes synthesized for MLC, TLC, and QLC NAND flash devices. The encoder circuit is designed using addition and multiplication tables derived from elements of synthesized SSRS codes. The Non-binary decoding procedure consists of the syndrome computation, Berlekamp -Massey algorithm, Chein search, and Forney's algorithm. The designed encoder requires 16% resources for MLC, 18% of resources for TLC, and 18% of resources for QLC. This research work has reported the design of very high rate (R ≥ 0.97) codes that can bring about significant improvements to the Undetected Bit Error Rate (UBER) even when the Raw Bit Error rate (RBER) values are significant (> 10-3). © 2013 IEEE.