Journal Articles

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884

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Subject: search.filters.subject.Crystal oscillators

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    Fast start crystal oscillator design with negative resistance control
    (Elsevier B.V., 2019) Kumar, P.; Rekha, S.
    Clock is an essential part of most of the integrated circuits as time base reference. It must be very accurate, highly reliable and readily available as soon as it is enabled. In all types of oscillator architectures, crystal oscillator is the most accurate and stable clock generator. But usually the crystal oscillator circuit suffers from slow startup. Therefore, it is essential to improve the startup time with optimally controlled crystal drive such that crystal drive power rating is not compromised. We propose a method that discusses about increasing the negative resistance during startup, using a startup circuit for fast start. Once the reliable startup is achieved, the negative resistance is decreased and the startup circuit is disconnected. The reduction in negative resistance is done with current steps and there are two ways in which it is achieved, the Digital control method and Analog control method. In digital control method, the current steps are timed at regular intervals and in analog control method, oscillator output amplitude is given as feedback to the startup circuit there by reducing the negative resistance. In the 32768 Hz real time clock generating oscillator, the startup time can be improved from 330 ms to 220 ms using the conventional startup method. With the proposed digital control method, lesser startup time of 160 ms is achieved and in analog control method it is further reduced to 120 ms. © 2018 Elsevier B.V.
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    FPGA Implementation of SSRS Codes for NAND Flash Memory Device
    (Institute of Electrical and Electronics Engineers Inc., 2024) Achala, G.; Nandana, S.; Jomy, F.; Girish, M.M.; Shripathi Acharya, U.S.; Srihari, P.; Cenkarmaddi, L.R.
    NAND flash memory is a non-volatile storage device that is extensively used in personal electronic gadgets, digital television, digital cameras, and many consumer/ professional electronics devices. Error control coding techniques have been incorporated to improve the integrity of information stored in these devices. We have synthesized the Subfield Subcodes of Reed Solomon codes (SSRS) for use on Multi-Level cell (MLC), Triple Level Cell (TLC), and Quadruple Level Cell (QLC) NAND flash devices. The primary advantage of these codes is that the codeword symbols can be correctly matched to the number of bits that can be stored in these multilevel cells. Deployment of these codes improves the integrity of information storage and useful life. This paper describes the implementation of the encoder and decoder of SSRS codes synthesized for MLC, TLC, and QLC NAND flash devices. The encoder circuit is designed using addition and multiplication tables derived from elements of synthesized SSRS codes. The Non-binary decoding procedure consists of the syndrome computation, Berlekamp -Massey algorithm, Chein search, and Forney's algorithm. The designed encoder requires 16% resources for MLC, 18% of resources for TLC, and 18% of resources for QLC. This research work has reported the design of very high rate (R ≥ 0.97) codes that can bring about significant improvements to the Undetected Bit Error Rate (UBER) even when the Raw Bit Error rate (RBER) values are significant (> 10-3). © 2013 IEEE.