Journal Articles

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884

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Author: search.filters.author.Sripati, U.Subject: search.filters.subject.Flash memory

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    Design and construction of BCH codes for enhancing data integrity in multi level flash memories
    (Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.
    Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.
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    High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices
    (2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.
    In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application. © 2012 Taylor & Francis.