Journal Articles

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884

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Author: search.filters.author.Jagabar Sathik, J.

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    A New Generalized Multilevel Converter Topology Based on Cascaded Connection of Basic Units
    (Institute of Electrical and Electronics Engineers Inc., 2019) Jagabar Sathik, J.; Shalchi Alishah, R.; Sandeep, N.; Hosseini, S.H.; Babaei, E.; Krishnasamy, K.; Yaragatti, U.R.
    In this paper, a new single-phase multilevel converter (MLC) topology based on the cascade connection of novel basic units is presented. The proposed basic unit generates 17-level output voltage waveform and can be extended for higher voltage levels by using a simple cascade connection. Both the proposed basic unit and cascaded topologies are compared with other state-of-the-art MLC topologies. From the comparison results, it will be shown that the proposed topology has several advantages such as the reduced number of power electronic components, lesser number of dc sources, and blocking voltage. Moreover, the proposed MLC has reduced power losses and improved efficiency. The operability and feasibility of the proposed converter are validated through extensive simulation and experiments. Finally, the corresponding results affirming the predominance of the proposed topologies are presented. © 2013 IEEE.
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    Modified Selective Harmonics Mitigation PWM for a Switched Diode Multilevel Inverter
    (IOP Publishing Ltd, 2021) Sahaya Ponrekha, A.; Jagabar Sathik, J.; Lakshmanan, P.; Singh, J.; Mani, L.; Mandal, A.; Madhavan, J.
    A modified selective harmonic mitigation (SHM) technique for multilevel inverters considering the RMS output voltage magnitude is presented. The harmonic contents in the output voltage of these inverters must satisfy the specified grid code requirement standards. In conventional SHM techniques, the firing angles of the multilevel inverters have been derived by taking into account grid code harmonic reduction standards. When the multi-level inverters are driven with these firing pulses generated, it results in reduction of the magnitude of the inverter output voltage. In order to overcome this issue of output voltage reduction, the modified SHM optimization problem includes another constraint on the RMS output voltage limits, which results in different set of firing angles. This facilitates the use of firing angles, which takes into account the grid code standards of harmonic mitigation without compromising the value of the RMS output voltage of the inverters. The proposal has been simulated and validated in MATLAB Simulink and the experimental results are obtained for a single-phase seven level inverter with Silicon made semiconductor switches. By using the proposed method, output voltage THD (upto 40th harmonics were considered) of 5.9% was obtained, which is well below the harmonic standards specified by EN 50160. © 2021 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.