Journal Articles
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884
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Item Performance analysis of 65 nm CMOS LNA using SSL technique for 5G cellular front-end receivers(Elsevier GmbH k.ernst@elsevier.com, 2020) R, V.; Gorre, P.; Song, H.; Kumar, S.This paper presents a performance analysis of a wideband low noise amplifier (LNA) that utilizes a 65 nm CMOS Samsung mm-wave process. The proposed CMOS LNA designed with new built-in techniques will overcome the challenges faced by device parasitic and electromagnetic (EM) losses. A suspended substrate line (SSL) is characterized and analyzed with its dual-band operation and achieves excellent EM compatibility. The traditional EM losses in bulk active and passive components have been incurred using built-in techniques to provide better linearity of LNA. The proposed mm-wave LNA enables it's each family component to avoid leakage of EM waves and its interconnected parasitic losses in layout. An SSL based parallel-series network is optimized to achieve a wide bandwidth of 26 GHz to 34 GHz. The full design of LNA achieves the highest peak gain of 25 dB by using proper 50 ? matching constraints over the wideband response of 27.8 GHz to 32.5 GHz. The fabricated chip of LNA is given a supply voltage of 1.2 V, and the calculated chip area is 0.35*0.22 mm2. The simulation and measurement results demonstrate the minimum noise figure of 2.5 dB and achieve the highest stability factor in the desired band of operation. The LNA also measured linearity with a 1 dB compression point where input power of ?19dBm has obtained at 30.5 GHz. © 2020 Elsevier GmbHItem A 61.2-dB?, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver(Springer, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-?m process. The TIA achieves a flat transimpedance gain of 61.2 dB? with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/?Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10?12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.Item A 64 ?dB?, 25 ?Gb/s GFET based transimpedance amplifier with UWB resonator for optical radar detection in medical applications(Elsevier Ltd, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.This work reports a novel Graphene Field Effect Transistor (GFET) based transimpedance amplifier (TIA) for optical radar detection in medical applications. Design-I includes a microstrip line (MSL) based UWB resonator circuit which enables the TIA design to operate in UWB range of frequency with high Q-factor. Design-II comprises MSL UWB resonator integrated stagger-tuned CR-RGC TIA which enhances the transimpedance limit and mitigates the effect of photodiode capacitance results in higher bandwidth performance. The proposed TIA realizes a 2.6 times lesser noise compared to the conventional CR-RGC TIA. A flat transimpedance gain of 64 ?dB? and ultra-low input-referred noise current density of 8.9 pA/?Hz are achieved using gain and noise optimization methods. Additionally, a dynamic range of 49 ?dB with a group delay variation (GDV) of ±25 ps is achieved over the entire UWB range. The TIA demonstrates a 25 ?Gb/s data rate while a bit-error-rate (BER) less than 10?10 is achieved. The chip occupies an area of 0.67?0.72 ?mm2 while consuming power of 19 ?mW under the supply voltage of 1.8 ?V. © 2021 Elsevier LtdItem Highly robust X-band quasi circulator-integrated low-noise amplifier for high survivability of radio frequency front-end systems(John Wiley and Sons Ltd, 2021) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.In this brief, an X-band quasi circulator (QC)-integrated low-noise amplifier (LNA) implemented in 65-nm Complementary Metal Oxide Semiconductor (CMOS) technology is presented. This work is the first QC-LNA for the X-band to the author's best knowledge, which achieves 30-dB flat gain in 8–12 GHz with only 0.5-dB variation across the band. This QC-LNA uses two-stage current reused techniques with variable impedance load. QC provides the minimum insertion loss of 0.9 dB with good return and isolation losses. Statistical analysis is presented for QC-LNA to predict the percentage error tolerance. Quasi-Newton (QN) control algorithm is used to optimize the parameter of the whole design. The design of experiment (DoE) is performed to claim the contribution towards gain, return loss, and noise figure. The proposed LNA measurement provides a minimum NF of 1 dB at 9.5 GHz, which remains less than 1.4 dB across 8–12 GHz. The fabricated LNA works with a supply voltage of 1.2 V and is unconditionally stable across the frequency. The calculated chip area is 0.84 × 0.52 mm2. This QC-LNA exhibits an input and output 1-dB compression point (IP1dB and OP1dB) of ?15 and +13.8 dBm, respectively. It also exhibits third-order input and output intercept point (IIP3 and OIP3) of +10 dBm and of +40 dBm, respectively. The proposed QC-LNA draws only 8.7 mA from 1.2 V. © 2021 John Wiley & Sons, Ltd.Item A novel wide bandwidth FBSSIR integrated low noise amplifier for satellite navigational receiver system(Elsevier Ltd, 2021) Vignesh, R.; Gorre, P.; Kumar, S.This paper presents a Folded Butterfly Stub Stepped Impedance Resonator (FBSSIR) integrated low noise amplifier (LNA) implemented using packaging technology for the satellite navigation receiver system. By employing a novel structural deformation of a stepped-impedance-resonator (SIR), the proposed FBSSIR is achieved with a more compact structure, controllable transmission zero, adjustable center frequency, and adjustable bandwidth. The designed FBSSIR acts as a filter, and the input-output matching network is integrated into the proposed core LNA circuit. The Design-of-experiment (DoE) analysis is performed to analyze the passive component's sensitivity becoming desensitized, while statistical analysis is presented for the proposed FBSSIR integrated LNA to predict the percentage error tolerance. Its measurement result provides gain above 22 dB in the wide bandwidth from 1.6 GHz to 2.5 GHz, minimum NF of 2.7 dB at 1.8 GHz, which varies from 3 dB to 4.5 dB. The calculated area of FBSSIR integrated LNA is 10.7 × 2 cm2, while LNA is 3.3 × 1.6 cm2. It exhibits an input and output 1-dB compression point (IP1dB & OP1dB) of ?23dBm and +2.3dBm. © 2021Item A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line(Institute of Electrical and Electronics Engineers Inc., 2022) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB OP1dB), third-order input output intercept point (IIP3 OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 $\times $ 0.92 mm2. © 2013 IEEE.Item A strip line technique based 1 Gb/s, 70-dB linear dynamic range transimpedance amplifier towards LiDAR unmanned vehicle application(Elsevier Ltd, 2022) Gorre, P.; Vignesh, R.; Kumar, S.1This work reports a Microstrip Line (MSL) based Dual-Gate MOSFET (DGMOSFET) Transimpedance amplifier (TIA) for LIDAR unmanned vehicle application under different weather conditions. TIA (Design-I) is proposed under normal weather, while TIA (Design-II) for foggy weather conditions. TIA (Design-I) employs a variable gain common gate topology with post-amplification, resulting in high gain, wide bandwidth, and high dynamic range (DR). TIA (Design-II) incorporates a series MSL section at the input of TIA (Design-I), which further enhances the bandwidth performance. TIA (Design-I) realizes a fractional bandwidth of 104.3% with a transimpedance gain of 100.4 dBΩ and low input-referred noise (IRN) density of 4.29 pA/√Hz. TIA (Design-II) achieves a fractional bandwidth of 178.4% with transimpedance gain, IRN, and DR of 100.42 dBΩ, 3.81 pA/√Hz, and 70 dB, respectively. TIA (Design-II) demonstrates a 1 Gb/s data rate with a bit-error-rate < 10−10. The TIA (Design-I) and TIA (Design-II) consume the power of 33 mW and 39 mW under the supply voltage of 2 V. © 2022 Elsevier LtdItem High-Performance Graphene FET Integrated Front-End Amplifier Using Pseudo-resistor Technique for Neuro-prosthetic Diagnosis(SpringerOpen, 2022) Naik, J.D.; Gorre, P.; Akuri, N.G.; Kumar, S.; Al-Shidaifat, A.D.; Song, H.A complex analysis of spike monitoring in neuro-prosthetic diagnosis demands a high-speed sub-nanoscale transistors with an advanced device technologies. This work reports the high performance of Graphene field-effect transistor (GFET) based front-end amplifier (FEA) design for the neuro-prosthetic application. The 9 nm Graphene FET device is optimized by characterization of transconductance and drain current towards high sensitivity and small factor. The proposed GFET-based FEA with pseudo-resistor technique demonstrates very high-input impedance in Tera-ohms that nullify the input leakage current. Here, gain-bandwidth product and noise optimization of GFET FEA enhances the overall gain with negligible noise. The proposed design operates at low voltage, further reduces the power consumption, and achieves less chip area in sub-nano size so it could be more suitable for implantable devices. The GFET-based FEA architecture achieves an action potential spike of 1.4 µV while the local field potentials spike of 1.8 mV. The proposed architecture is implemented in Advanced Design System using the design kit of the GFET process. Power consumption of 3.14 µW is observed with a supply voltage of 0.9 V. The simulated and experimental results of the proposed design achieve an input impedance of 2 TΩ with excellent noise performance over a wideband of 13.85 MHz. The proposed work demonstrates better neural activity sensing when compared to the state-of-the-artwork, which could be highly beneficial for future neuroscientists. © 2022, The Korean BioChip Society.Item A wideband, 25/40dBm high I/O power GaN HEMT ultra-low noise amplifier using even-odd mode techniques(Elsevier Ltd, 2022) Gupta, M.P.; Gorre, P.; Kumar, S.; Nulu, V.This paper presents a performance analysis of the low noise amplifier (LNA) for the first time using even-odd mode matching techniques in Gallium Nitride (GaN) HEMT Technology for marine communication. The proposed GaN LNA circuit consists of broadband stage I, main amplifier, and inverted broadband stage II, which provides a high input/output power, and ultra-low noise over wide bandwidth ranging from 0.5 GHz to 2.7 GHz with fractional impedance bandwidth of 138%. Broadband Stage I and Inverted broadband stage II are employed to provide input/output impedance matching transformation. The proposed LNA circuit with the incorporation of input/output broadband stages relax a 50Ω matching constraints and achieved high input and output power with good stability. The GaN HEMT LNA is analyzed and simulated using the RF simulator (ADS tool). The proposed GaN HEMT LNA is fabricated on RT Duroid substrate using Microwave Integrated Circuit (MIC) technology. The proposed LNA achieves a measured gain of 16 dB, while the simulated one is 17 dB with good insertion loss. An ultra-low noise figure of 0.6 dB flat is achieved over a wide bandwidth. In addition, the high output power is achieved 40dBm while input power is 25dBm which could overcome weak signal strength received by RF receiver for marine communication. A stability factor greater than one is achieved over a broad band ranging from 0.5 GHz to 2.7 GHz. The fabricated GaN HEMT LNA circuit has consumed power of 120 mW under a supply of 28 V. The area of the fabricated RF GaN HEMT LNA is 32 × 26 mm2. © 2022 Elsevier LtdItem A 2.71-pA/√Hz ultra-low noise, 70-dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth(John Wiley and Sons Ltd, 2023) Gorre, P.; Vignesh, R.; Kumar, S.; Song, H.; Roy, G.M.Recent advancements in the area of telemedicine have focused on remote patient monitoring services as a new frontier in medical applications. The present work reports a 65-nm complementary metal–oxide–semiconductor (CMOS)-based transimpedance amplifier (TIA) in an optical radar system for non-contact patient monitoring. A T-shaped microstrip line (MSL) integrated with variable gain common source TIA using MSL peaking technique and off-chip post-amplification integration is a newly proposed architecture to achieve a ultra-low noise, high dynamic range (DR) and high figure of merit over broadband than a traditional TIAs. First, the integrated T-shaped MSL develops an additional resonant frequency that resonates with a photodiode capacitance improving the bandwidth performance at higher Q values. Second, the shunt MSL peaking technique that introduces an additional conjugate pole-pair that cancels the effect of input capacitance helps to further improve the bandwidth of the TIA. Finally, an active feedback concept achieves a wide linear dynamic range enabling high TIA detectability. The proposed TIA realizes an impedance bandwidth of 770 MHz ranging from 7.12 to 7.89 GHz with a transimpedance gain of 105.1 dBΩ and ultra-low input-referred noise (IRN) density of 2.71 pA/√Hz. A high linear DR of 70 dB is achieved by employing a variable gain control scheme with a low group delay variation of 0.81 ns. The proposed work demonstrates a 1-Gb/s data rate while a bit-error rate less than 10−12 is achieved. The TIA consumes a power of 0.82 mW under the supply voltage of 1.2 V. © 2022 John Wiley & Sons Ltd.