Journal Articles
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884
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Item Distributed video coding based on classification of frequency bands with block texture conditioned key frame encoder for wireless capsule endoscopy(Elsevier Ltd, 2020) Sushma, B.; Aparna., P.Wireless capsule endoscopy (WCE) has provided remarkable improvement in diagnosing gastrointestinal disorders by scanning the entire digestive tract. The system still need refinement, to upgrade the quality of images, frame rate and battery life. The principal component of the system that can address these issues is low complexity video compressor. Motivated by low computational complexity requirements of WCE video encoding, this paper presents a distributed video coding framework based on frequency bands classification. The lower frequency bands are used to generate good quality side information (SI) as they exhibit high temporal correlation. This reduces the complexity of hash generation at the encoder, thus eliminating the latency in SI creation. Apart from this, SI creation involves only a simple block search and doesn't depend on Wyner–Ziv (WZ) bands. Also different approach for distributed coding of sub-sampled chroma components of WZ frame is proposed. Low complexity JPEG based key frame encoding is proposed that take advantage of WCE image textural properties to reduce the complexity of encoding smooth blocks by 81% at the quantization and encoding stage. Other novel features include use of discrete Tchebichef transform (DTT), Golomb–Rice code for entropy coding. Performance evaluation shows that the proposed method achieves 60% improvement in compression over Motion JPEG with low computational complexity. © 2020 Elsevier LtdItem An efficient parallel-pipelined intra prediction architecture to support DCT/DST engine of HEVC encoder(Springer Science and Business Media Deutschland GmbH, 2022) Poola, L.; Aparna., P.The complexity of intra prediction in high-efficiency video coding (HEVC) is increased due to the addition of five variable sized prediction units (PUs) and 35 directional predictions. In this work, we propose an efficient parallel-pipelined architecture that can process 8 samples in parallel for every clock cycle. The functional units needed to predict the PU samples work in a pipelined fashion. With this balanced combination of parallel-pipelined structure, we are able to achieve higher throughput with limited hardware resources than existing literature works. The samples are processed row-wise, so that they can be directly transform coded, thus eliminating the need for an intermediate memory buffer of 8 K between the two modules. A compact reconfigurable reference buffer of size 0.8 KB is incorporated to reduce the read-write latency associated with reference samples’ fetching. A dedicated module for arithmetic operations is used in the intra engine that ensures the reuse of multipliers to increase the hardware efficiency. The architecture so designed supports all the PU sizes and directional modes. The proposed design is tested and implemented on a field-programmable gate array (FPGA) platform operating at 150 MHz frequency to achieve 8 samples throughput with a hardware cost of 16.2 K Look-Up Tables (LUTs) and 5.7 K registers to support HD 4 K real-time video encoding applications. © 2022, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.Item Hardware Efficient Integrated In-loop Filter for HEVC Encoder(Taylor and Francis Ltd., 2024) Poola, L.; Aparna., P.The deblocking filter (DF) and the sample adaptive offset (SAO) filter, which aids in enhancing the subjective quality of the image, make up the in-loop filter of the high-efficiency video coding (HEVC) encoder and decoder. The in-loop filter significantly increases the computational load on the HEVC encoder. It is challenging to design an in-loop filter on hardware that can handle intensive computations while using the least amount of on-chip memory, taking external memory traffic and dependencies simultaneously delivering high throughput to support Ultra HD video applications. The proposed design employs the following strategies to address these issues. This work proposes an address generation technique for pipelined horizontal and vertical filtering in DF, that avoids a transpose buffer which otherwise is required. This enables easy pipelining and parallelization thus improving throughput while reducing the on-chip memory utilization. A simplified SAO filter with parallel-pipelined processing is included in the design. These features enable the design to support ultra-HD 7680 (Formula presented.) 4320 @ 40 fps video applications. The proposed hardware architecture has a total gate count of 7.73 K LUTs and 2.8 K slice registers, and it is implemented on a 28 nm field programmable gate array (FPGA) platform. © 2024 IETE.