Browsing by Author "Sridharan, S."

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    An FPGA based embedded sytems for online monitoring and power management in a standalone micro-grid
    (wiley, 2022) Dastagiri Reddy, B.D.; Venkatraman, K.; Selvan, M.P.; Sridharan, S.
    The amalgamation of numerous renewable sources to fulfill the energy demands of the consumers in distant areas with better reliability is a significant challenge because of unpredictable and fluctuating nature of renewable sources. Hence, An effective micro-grid control is required to accomplish the power balance among the load demand and generated power. In this work, A Field Programmable Gate Array (FPGA) based embedded system for online monitoring and power management is proposed for a standalone micro-grid. The developed standalone micro-grid consists of wind energy and solar energy as renewable sources, Diesel generator as a backup supply, And battery bank as storage unit. An algorithm is developed using two Field Programmable Gate Array (FPGA) controllers namely source FPGA controller and load FPGA controller implemented as an embedded system connected through an Ethernet interface with separate source control and load control features. The load FPGA controller provides load management (connecting/ disconnecting non-critical loads) based on the available power and load demand. The source FPGA controller provides source management by controlling the renewable energy sources and dump load. Finally, To monitor the electrical parameters and statuses of various energy sources (wind and solar), Loads (critical and noncritical loads) and storage unit (battery bank) an online monitoring system is developed without the need of a dedicated personal computer. This work has been developed in such a way that it is replicable on the large scale in the field. © 2022 Scrivener Publishing LLC. All rights reserved.
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    NoC based distributed partitionable memory system for a coarse grain reconfigurable architecture
    (2011) Tajammul, M.A.; Shami, M.A.; Hemani, A.; Sridharan, S.
    This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling capability. The proposed interconnect which enables the interaction between existing partition of computation fabric and the distributed memory system is programmable and partitionable. The system can modify its memory to computation element ratio at runtime. The interconnect can provide multiple interfaces that can support upto 8 GB/s per interface. © 2011 IEEE.