Browsing by Author "Sreelekha, N."

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    FPGA Implementation of Moving Target Indicator Filter for FMCW Radar Data
    (Institute of Electrical and Electronics Engineers Inc., 2023) Sreelekha, N.; Vandana, G.S.; Srihari, P.; Leelarani, V.; Raju, M.K.; Sreenivasula Reddy, T.S.
    This study examines several digital finite impulse response (FIR) filter approaches for moving target indication (MTI) employing short-range FMCW radar sensors. The FIR filters can filter out low doppler shift responses from undesirable stationary targets. A 77 GHz AWR1642 FMCW radar sensor and a DCA1000 data capture card are used to build a hardware configuration. A single data frame (samples × chirps) containing a target approaching the radar is been considered. The recorded radar is preserved in a 256x64 matrix of in-phase and quadrature-phase components, which is then processed using various digital filters. The radar provides insights into doppler characteristics for the observations. This study proposes designing and implementing a two-tap and a three-tap FIR filter-based MTI processing module to reduce static targets. The VLSI DSP pipelining approach is deployed to improve filter performance regarding critical path delay and throughput. © 2023 IEEE.
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    MTI Filter DSP Architectures in FMCW radar Framework for ADAS Applications
    (Institute of Electrical and Electronics Engineers Inc., 2023) Sreelekha, N.; Vandana, S.G.; Leelarani, V.; Srihari, P.; Pardhasaradhi, B.
    The digital Finite Impulse Response (FIR) filter emerges as a highly promising solution for enhancing Moving Target Indication (MTI) capabilities, particularly within the short-range Frequency-Modulated Continuous-Wave (FMCW) Radar framework. FIR filters prove instrumental in effectively filtering out low Doppler shift responses originating from stationary targets, thus improving radar performance in detecting moving objects. Milli-meter-wave Radar sensor AWR1642 of 77 GHz from Texas Instruments and a DCA1000 EVM capture card are used to record real-time data with moving target, which is then processed using high-speed data converter pro (HSDC) software focusing on the detection and tracking of moving targets. The frames of complex data from radar processing through various MTI FIR digital filters. This study delves into a range of VLSI Digital Signal Processing (DSP) techniques, including pipelining, parallel processing, broadcast structures, and retiming, all aimed at enhancing filter performance. These FIR structures are implemented using the Xilinx synthesis tool and deployed on the ZYNQ7 ZC702 FPGA board and the rest of the radar algorithm works on CPU in SoC configuration. Our experimental findings highlight the efficacy of retiming structures in optimizing pipeline delays, leading to reduced latency in the filtering process. This acceleration of MTI in SoC works in realtime, demonstrates substantial advantages for Advanced Driver Assistance Systems (ADAS) applications. It is characterized by a compact footprint, low power consumption, and high processing speed, making it a strong candidate for deployment in ADAS solutions. © 2023 IEEE.