Browsing by Author "Soorya Krishna, K."

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Estimation of interconnect metrics using state space approach
(2010) Soorya Krishna, K.; Pramod, M.; Bhat, M.S.
In this paper, we propose models for single and coupled on-chip global interconnect lines by distributed RLGC parameters using state space approach. Models for single and coupled lines are validated by comparing with SPICE simulations. Interconnect performance metrics are obtained from the proposed models for 65 nm, 90 nm, 130 nm and 180 nm technology nodes based on PTM values. In case of coupled interconnect lines, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and illustrated by applying our modeling approach to four coupled interconnect lines. Â©2010 IEEE.
Modelling of single, coupled, L and T type interconnects using state space approach
(Inderscience Publishers, 2009) Soorya Krishna, K.; Pramod, M.; Bhat, M.S.
In this paper, we propose models for single, coupled, L and T type on-chip global interconnect lines. Generalised models for different interconnect geometries are formed by distributed RLGC parameters using state space approach. Interconnect delay for a single interconnect line is estimated using our model and compared with other models. It is found that the error in the estimation of the delay is less in our model. Also interconnect performance metrics for the proposed models are obtained for 65 nm, 90 nm, 130nm and 180nm technology nodes based on Predictive Technology Model (PTM) values. In case of coupled, L and T section interconnects, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and can be used to characterise any interconnect structure. Further, the state matrices for any length of interconnect can be obtained by considering suitable number of rlgc segments. Copyright © 2009 Inderscience Enterprises Ltd.
Performance enhancement in high speed on-chip interconnect lines
(2010) Soorya Krishna, K.; Bhat, M.S.
An interconnect line along with a series inductor can be used as a resonant network for transmitting high frequency data/clock in an integrated circuit. In this paper, the design of an active inductor circuit and its use in a global interconnect line to form a resonant network for reducing interconnect delay and area is described. An active inductor in place of on-chip passive inductor reduces interconnect latency by 38% and area by 300 times at an operating frequency of 2 GHz in 0.18 Î¼m technology. Monte Carlo simulations are carried out to find the range of interconnect delay variations and output voltage fluctuations due to process and mismatch variations in the active inductor circuit. Â©2010 IEEE.