Browsing by Author "Song, H."

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A 0.15 μm GaN HEMT device to circuit approach towards dual-band ultra-low noise amplifier using defected ground bias technique
(Elsevier GmbH, 2023) Gupta, M.P.; Kumar, S.; Elizabeth Caroline, B.; Song, H.; Kumar, V.; Gorre, P.
This work presents a GaN HEMT device to circuit approach towards low noise amplifier (LNA) using defective ground bias (DGB) technique. This is the first MMIC GaN HEMT LNA design to offer dual-band of operation in both L and S-bands to the author's best knowledge. The proposed 0.15-μm GaN HEMT device fabrication achieves a high output power of 20 W using slot radiation phenomenon. The proposed DGB technique consists of gate and drain biasing topologies which achieves a dual-band of operation using microwave approach. The DGB technique is incorporated into GaN HEMT LNA which achieves high input and output power with good stability. To achieve an optimal noise, high I/O power, and almost flat gain at both L and S-bands, the defective ground structure of bias topologies is modeled and optimized. An artificial ground defect is created to offer resonant properties for the DGS of a microstrip line, which utilizes frequency-selective properties to improve the performance of the LNA circuit by suppressing the harmonics and scaling the size. The dedicated LNA shows the benefits of compact size, extremely low noise figure of 0.74/1.6 dB, high output power of 44 dBm and nearly flat gain of 14/11 dB at 1.17/2.49 GHz with the unique methodologies suggested. The compact GaN HEMT LNA could overcome the weak signal strength received by RF receiver for smart rail transport system. © 2023 Elsevier GmbH
A 0.5–5 Gb/s Wide Range, 160 fJ/Pulse Fully Integrated 13th-Order CMOS IR-UWB Transmitter for Wireless Capsule Endoscopy Systems
(John Wiley and Sons Ltd, 2025) Akuri, N.; Kumar, K.; Kumar, S.; Nikhil, K.S.; Song, H.
This paper proposes a novel technique based fully integrated 13th-order derivative CMOS impulse-radio ultrawideband (IR-UWB) transmitter with wide range of adaptive data rates for wireless capsule endoscopy systems (WCE). The proposed IR-UWB transmitter involves BPSK modulator-integrated RF power amplifier (PA) approach for WCE in first time as per author's best knowledge. The CMOS BPSK modulator with resonator technique generates 13th-order Modulated Gaussian pulse without the pulse generator. It has a peak-to-peak value of 25 mV and PSD level of ?72.60 dBm/MHz, data rate variability from 500 Mbps to 5 Gbps. The BPSK modulator with resonator is designed by time constant analysis in first time. In addition, a proposed CMOS PA is designed using four stacked transistors, which achieves a high output power as well as high efficiency for entire frequency band of operation from 3 to 16 GHz and wide impedance matching. The PA achieved an excellent gain of 16.55 dB with gain ripple of 0.25 dB only. Moreover, the PA achieved the saturated output power of 18.2 to 19.3 dBm with OP1dB of 15.96 to 16.72 dBm across entire bandwidth. Without violating FCC guidelines, PA strengths both peak-to-peak values, and PSD level of BPSK modulated signal to 80 mV and ?46.42 dBm/MHz. An IR-UWB transmitter has been implemented and fabricated using 65-nm CMOS Process, which consumes of only 160 fJ/pulse for generating Gaussian pulses order ranging from third-order to more than 13th-order at various data rates. © 2025 John Wiley & Sons Ltd.
A 2.71-pA/√Hz ultra-low noise, 70-dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth
(John Wiley and Sons Ltd, 2023) Gorre, P.; Vignesh, R.; Kumar, S.; Song, H.; Roy, G.M.
Recent advancements in the area of telemedicine have focused on remote patient monitoring services as a new frontier in medical applications. The present work reports a 65-nm complementary metal–oxide–semiconductor (CMOS)-based transimpedance amplifier (TIA) in an optical radar system for non-contact patient monitoring. A T-shaped microstrip line (MSL) integrated with variable gain common source TIA using MSL peaking technique and off-chip post-amplification integration is a newly proposed architecture to achieve a ultra-low noise, high dynamic range (DR) and high figure of merit over broadband than a traditional TIAs. First, the integrated T-shaped MSL develops an additional resonant frequency that resonates with a photodiode capacitance improving the bandwidth performance at higher Q values. Second, the shunt MSL peaking technique that introduces an additional conjugate pole-pair that cancels the effect of input capacitance helps to further improve the bandwidth of the TIA. Finally, an active feedback concept achieves a wide linear dynamic range enabling high TIA detectability. The proposed TIA realizes an impedance bandwidth of 770 MHz ranging from 7.12 to 7.89 GHz with a transimpedance gain of 105.1 dBΩ and ultra-low input-referred noise (IRN) density of 2.71 pA/√Hz. A high linear DR of 70 dB is achieved by employing a variable gain control scheme with a low group delay variation of 0.81 ns. The proposed work demonstrates a 1-Gb/s data rate while a bit-error rate less than 10−12 is achieved. The TIA consumes a power of 0.82 mW under the supply voltage of 1.2 V. © 2022 John Wiley & Sons Ltd.
A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems
(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.
In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023
A 28-32GHz CMOS LNA with broadband approach for 5G Mm-wave communication cells
(Institute of Electrical and Electronics Engineers Inc., 2019) Vignesh, R.; Gorre, P.; Kumar, S.; Song, H.
This paper first time reports a wideband low noise amplifier (LNA) with achievable minimum atmospheric absorption frequency band for 5G millimeter wave communication cells. A novel suspended substrate line based parallel-series network is optimized and analyzed that demonstrates a wideband response. The proposed LNA consists of two stage Cascode topology with incorporated parallel-series network and microwave components that provides broadband ranging from 28GHz to 32GHz. A full of two stage Cascode LNA overcoming the traditional mismatching constraints with consideration of suspended substrate lines (SSL) and Tee-junction in the proposed design. It is observed that suspended lines reduce parasitic and bulk effects of devices and enables LNA to provide broadband communication for 5G macro and micro cells. The proposed design is realized using RF 65nm Magna Hynix CMOS process with layout cell. The simulation results reveals that 28GHz-32GHz wide band with maximum forward gain of 25dB. The minimum noise figure of 2.5dB is achieved with optimization of passive components. The input impedance (real and imaginary) and smith chart realization for LNA provides satisfactory performance. Â© 2019 IEEE.
A 61.2-dB?, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver
(Springer, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.
This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-?m process. The TIA achieves a flat transimpedance gain of 61.2 dB? with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/?Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10?12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.
A 64 ?dB?, 25 ?Gb/s GFET based transimpedance amplifier with UWB resonator for optical radar detection in medical applications
(Elsevier Ltd, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.
This work reports a novel Graphene Field Effect Transistor (GFET) based transimpedance amplifier (TIA) for optical radar detection in medical applications. Design-I includes a microstrip line (MSL) based UWB resonator circuit which enables the TIA design to operate in UWB range of frequency with high Q-factor. Design-II comprises MSL UWB resonator integrated stagger-tuned CR-RGC TIA which enhances the transimpedance limit and mitigates the effect of photodiode capacitance results in higher bandwidth performance. The proposed TIA realizes a 2.6 times lesser noise compared to the conventional CR-RGC TIA. A flat transimpedance gain of 64 ?dB? and ultra-low input-referred noise current density of 8.9 pA/?Hz are achieved using gain and noise optimization methods. Additionally, a dynamic range of 49 ?dB with a group delay variation (GDV) of ±25 ps is achieved over the entire UWB range. The TIA demonstrates a 25 ?Gb/s data rate while a bit-error-rate (BER) less than 10?10 is achieved. The chip occupies an area of 0.67?0.72 ?mm2 while consuming power of 19 ?mW under the supply voltage of 1.8 ?V. © 2021 Elsevier Ltd
A 73% PAE, Highly Gain Inverse Class-F Power Amplifier for S-Band Applications
(Springer Science and Business Media Deutschland GmbH, 2021) Naik, J.D.; Gorre, P.; Kumar, R.; Kumar, S.; Song, H.
This paper proposes a continuous-mode inverse Class F power amplifier (PA) achieving wide bandwidth, high output power, and high efficiency. This work includes transmission line-based output/input matching networks and single-ended topology. The main focus of the work is to achieve a high gain with wide bandwidth. The proposed structure incorporates a termination of even and odd harmonics to deliver voltage and current waveform isolation with minimal matching network (MN) design complexities. The analyses simulated in Keysight Technologies Advanced Design System (ADS), which results in a wideband PA design. The results are quantified by using high power-added efficiency (PAE) and output power. PAE of 72.6% and output power more than 41Â dBm obtained over wide bandwidth 2â€“4.2Â GHz at âˆ’3Â dB gain compression. The proposed PA could overcome the traditional performance and utilize for green communication. Â© 2021, Springer Nature Singapore Pte Ltd.
A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters
(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.
This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
A Compact Dual-band Hat-Shaped Antenna with Band-Specific Behavior Using Harmonic Mixer for Passive Neural Monitoring
(Institute for Ionics, 2024) Gopavajhula, D.S.; Kumar, S.; Narasimhadhan, A.V.; Song, H.
This work proposes a hat-shaped dual-band antenna with band-specific behavior using a harmonic mixer for the passive wireless neural monitoring system. The antenna is designed to work in coherence with a harmonic mixer of 2nd order. The antenna covers a volume of 16 × 16 × 1.6 mm3. The performance of the antenna is found to be satisfactory by conducting experiments using both homogeneous and heterogeneous media mimicking human tissue after covering it with a biocompatible PDMS layer. The lower and higher resonant bands extend from 3.75 to 3.9 GHz and 7.05 to 8.2 GHz, respectively, supporting communication at high data rates up to 20 Mbps. A directive gain of 1.29 dB in the lower band and 1.39 dB in the higher band makes it a good choice for implantable medical devices. A six-layer head model was considered for SAR evaluation with a penetration depth of 10 mm for safe operation as per IEEE C95.1-1999 standard. Based on this simulation, the maximum input power that can be fed to the antenna for safe operation is found to be 8.46 mW. The link budget analysis reveals that a satisfactory communication link may potentially be established up to a distance of 7 and 1.5 m between implantable and interrogator antennae with corresponding data rates of 1 Mbps and 20 Mbps, respectively. © The Author(s), under exclusive licence to Shiraz University 2023.
A Conceptual Investigation at the Interface between Wireless Power Devices and CMOS Neuron IC for Retinal Image Acquisition
(MDPI, 2020) Al-Shidaifat, A.; Kumar, S.; Chakrabartty, S.; Song, H.
In this paper, a conceptual investigation of the interface between wireless power devices and a retina complementary metal oxide semiconductor (CMOS) neuron integrated circuit (IC) have been presented. The proposed investigation consists of three designs: design-I, design-II, and design-III. Design-I involves a slotted loop monopole antenna as per American National Standards Institute (ANSI) guidelines, which achieve an ultra-wide band ranging from 3.1 GHz to 10.6 GHz. The biocompatible antenna is made on silicon-nitride substrate using on-wafer packaging technology and it is used as a receiver device. The performance of antenna provides a wideband, sufficient power to receive, and low losses due to the avoidance of printed circuit board (PCB) fabrication. A CMOS based multi-stack power harvesting circuit achieves the output power ranging from 4 mW to 2.7 W and corresponds from the selected Radio Frequency (RF) bands of loop antenna is exhibited in design-II. The power efficiency of 40% to 82%, with respect to output powers of 4 mW to 2.7 W, is achieved. Design-III includes a CMOS based retina neuron circuit that employs a dynamic feedback technique and support to achieve the number of read-out spikes. At the end of the interface between wireless power devices and a CMOS retina neuron IC, 50 mV read-out spikes are achieved, with varying light intensity, from 0 mW/cm2 to 2 mW/cm2. The proposed design-II and design-III are implemented and fabricated using commercial CMOS 0.065 µm, Samsung process. The antenna and RF power harvesting IC could be placed on a contact lens platform while retina neuron IC can be implanted after ganglions cells inside the eye. The antenna and harvesting IC are physically connected to the retina circuit in the form of light. This conceptual investigation could support medical professionals in achieving an interfacing approach to restore the image visualization. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.
A high efficiency on-chip reconfigurable Doherty power amplifier for LTE communication cells
(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2018) Kumar, R.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.
In this paper, a high efficiency on-chip reconfigurable Doherty power amplifier (DPA) with proposed topology is proposed for LTE or 4G communication cells. The proposed DPA consists of input driver topology, hybrid coupler, asymmetric amplifiers, and 1:1 balun filtered network. The proposed input driver circuit provides wide amplified signal operation within range of 2.3GHz to 6GHz with flat gain of 33 dB. The amplified signal is unsteadily divided into two paths toward the carrier and the power amplifier by 900 hybrid couplers and demonstrates 27.6 dB and 28.3 dB of gain along with 83.2% and 84.5% of power added efficiency at average output power of 40 dBm. The high efficiency and almost flatness in gain stability of proposed DPA providing better solution in order to overcome the interference and the broadband issues for LTE communication cells. The balun-filtered network is employed for combined the two outputs of carrier and peak amplifiers that provides more uniform desired band of operation in the frequency responses. The proposed DPA circuit are implemented and optimized by using advanced design RF simulator platform. The fabricated chip is made by using 0.13 ?m GaN HEMT on Si-Nitride monolithic microwave integrated circuit die process. The fabricated chip of DPA provides 85% of PAE with 28 dB gain which are made close agreement with simulation results. The size of chip is 2.8*1.2mm2 which occupies less die area as compared to existing DPAs. © 2018 Wiley Periodicals, Inc.
A High-Sensitive High-Input Impedance CMOS Front-End Amplifier for Neural Spike Detection
(Springer Science and Business Media Deutschland GmbH, 2023) Naik, J.D.; Gorre, P.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.
Neural spikes detection and monitoring for neuro-prosthetic applications require an efficient and robust front-end amplifier (FEA), which regulates the fidelity of the neural signal. This paper presents neutralization and bootstrapping techniques to overcome the input leakage currents produced by amplifiers of the input bias network. In addition, a pseudo-resistor technique ensures the FEA maintains a high-input impedance. The CMOS-based FEA architecture is executed in the advanced design system with the design kit of the CMOS process. The proposed design achieves a high-input impedance of 0.5 TÎ© with a maximum simulation gain of 66.2Â dB. The overall power consumption of the topology is observed as 2.6Â ÂµW with a power supply voltage of 0.9Â V. The simulated noise performance of 6 nV/âˆšHz at 1Â kHz demonstrates a high-sensitive design compared to the previous works. It is highly recommended for succeeding neuro-prosthetic applications. Â© 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line
(Institute of Electrical and Electronics Engineers Inc., 2022) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.
This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB OP1dB), third-order input output intercept point (IIP3 OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 $\times $ 0.92 mm2. © 2013 IEEE.
A Low-Power Highly Efficient DCâ€“DC Buck Converter Using PWM Technique
(Springer Science and Business Media Deutschland GmbH, 2023) Islam, M.T.; Haque, M.N.; Khan, S.R.; Naik, J.D.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.
Integrated digital circuits (IDCs) have become a popular option for DCâ€“DC buck converters. This article describes a novel CMOS DCâ€“DC buck converter architecture that leverages pulse-width modulation (PWM) for low-power technology. Double delay lines are used in the PWM power consumption which is minimized throughout design and improve unstable voltage while increasing resolution. The functioning of PWM is described using an algorithm developed. Under the working frequency of 100Â kHz, the promising findings suggest that the power consumption is reduced to 1.17Â W while taking up less space. With a current, the DCâ€“DC buck converter using PWM has a high efficiency of 92.2% across a power range of 4â€“10Â mA. Compared to traditional converters, our PWM approach reduces ripple voltage by 48% and allows in order to create within a DCâ€“DC converter in a smaller chip area. Â© 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband
(Elsevier GmbH, 2024) Gupta, M.P.; Kumar, S.; Naik Jatoth, D.; Gorre, P.; Song, H.
This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs. © 2024 Elsevier GmbH
A novel chaotic modulation approach of packaged antenna for secured wireless medical sensor network in E-healthcare applications
(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2020) Jayawickrama, C.; Kumar, S.; Chakrabartty, S.; Song, H.
This article first time reports the chaotic modulation approach toward RF signal processing for secured wireless medical sensor network (WMSN) in E-healthcare applications. A Lorenz based chaotic modulation approach is implemented which provides lowest bit error rate (BER). The definite analytical expressions for BER in a differential chaos-shift keying (DCSK) modulation scheme is derived and it predicted good correlation between simulated and theoretical. It is observed that proposed Lorenz chaos-based DCSK modulation scheme is a potential candidate to provide high security in the patient data for WMSN. An off-body UWB slotted antenna is designed which could avoid limitation of short-range distance like implanted ones. The entire work includes numerical, simulated and experimental data in three phases. In first phase, Lorenz chaotic oscillator with electronics compatibility is executed which acts as data acquisition unit and demonstrates two-dimensional and three-dimensional chaos attractors. While in the second phase, analysis of BER achieves value of less than 10?4 by providing pseudorandom bit sequence at 5 Gb/s. A chaos modulated envelope using Lorenz based DCSK modulation is obtained by delay element ?. Finally, the third phase is designed on-wafer off-body antenna and demonstrates 3.1 to 10.6 GHz UWB toward RF signal processing in E-healthcare applications. © 2019 Wiley Periodicals, Inc.
A novel characterization and performance measurement of memristor devices for synaptic emulators in advanced neuro-computing
(MDPI AG indexing@mdpi.com Postfach Basel CH-4005, 2020) Al-Shidaifat, A.; Chakrabartty, S.; Kumar, S.; Acharjee, S.; Song, H.
The advanced neuro-computing field requires new memristor devices with great potential as synaptic emulators between pre-and postsynaptic neurons. This paper presents memristor devices with TiO2 Nanoparticles (NPs)/Ag(Silver) and Titanium Dioxide (TiO2) Nanoparticles (NPs)/Au(Gold) electrodes for synaptic emulators in an advanced neurocomputing application. A comparative study between Ag(Silver)-and Au(Gold)-based memristor devices is presented where the Ag electrode provides the improved performance, as compared to the Au electrode. Device characterization is observed by the Scanning Electron Microscope (SEM) image, which displays the grown electrode, while the morphology of nanoparticles (NPs) is verified by Atomic Force Microscopy (AFM). The resistive switching (RS) phenomena observed in Ag/TiO2 and Au/TiO2 shows the sweeping mechanism for low resistance and high resistance states. The resistive switching time of Au/TiO2 NPs and Ag/TiO2 NPs is calculated, while the theoretical validation of the memory window demonstrates memristor behavior as a synaptic emulator. Measurement of the capacitor-voltage curve shows that the memristor with Ag contact is a good candidate for charge storage as compared to Au. The classification of 3 x 3 pixel black/white image is demonstrated by the 3 x 3 cross bar memristor with pre-and post-neuron system. The proposed memristor devices with the Ag electrode demonstrate the adequate performance compared to the Au electrode, and may present noteworthy advantages in the field of neuromorphic computing. © 2019 by the authors. Licensee MDPI, Basel, Switzerland.
A review on functional polymer-clay based nanocomposite membranes for treatment of water
(Elsevier B.V., 2019) Buruga, K.; Song, H.; Shang, J.; Bolan, N.; Kalathi, J.T.; Kim, K.-H.
Water is essential for every living being. Increasing population, mismanagement of water sources, urbanization, industrialization, globalization, and global warming have all contributed to the scarcity of fresh water sources and the growing demand of such resources. Securing and allocating sufficient water resources has thus become one of the current major global challenges. Membrane technology has dominated the field of water purification due to its ease of usage and fabrication with high efficiency. The development of novel membrane materials can hence play a central role in advancing the field of membrane technology. It is noted that polymer-clay nanocomposites have been used widely for treatment of waste water. Nonetheless, not much efforts have been put to functionalize their membranes to be selective for specific targets. This review was organized to offer better insights into various types of functional polymer and clays composite membranes developed for efficient treatment and purification of water/wastewater. Our discussion was extended further to evaluate the efficacy of membrane techniques employed in the water industry against major chemical (e.g., heavy metal, dye, and phenol) and biological contaminants (e.g., biofouling). © 2019 Elsevier B.V.
A Wideband Microstrip Line-Based Balun Structure for High Power Amplifier Applications
(Springer Science and Business Media Deutschland GmbH, 2023) Gupta, M.P.; Gorre, P.; Kumar, S.; Song, H.
This paper proposes a balun matching technique to achieving a high output power and wide bandwidth. The proposed structure includes microstrip transmission line-based even and odd mode-matching circuits. A three-port unipolar microstrip line is designed to transform the balanced load termination to 50 Î© unbalanced port impedance. The proposed network design is based on real symmetrical four port network with open ended transmission line is inserted between the middle of the structure. To improve the isolation, transmission coefficient parameter and match the 50 Î© termination, a resistive network is inserted between the two balanced ports. The proposed structure is simulated in Keysight Technologies Advanced Design System (ADS), fabrication is done by using 0.51Â mm RT Duriod substrate alignments. To verify the design concept, first of all, a wideband microstrip matching technique is designed and characterized at the frequency of L5 band (1.17Â GHz). Then a prototype of microstrip transmission line-based wideband balun matching circuit is designed and fabricated. Analytical design equations have been derived for the even mode as well as odd mode techniques which satisfied the results. The proposed balun could overcome power loss mechanism over traditional transmission line structures and can utilize for high power application. Â© 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.