Browsing by Author "Shankarananda, B."

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Enhancing the error-correcting capability of imai-kamiyanagi codes for data storage systems by adopting iterative decoding using a parity check tree
(2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
A novel low-complexity, soft decision technique which allows the decoding of distance-5 double error-correcting Imai-Kamiyanagi codes by using a parity check tree associated with the Tanner graph is proposed. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. For the AWGN channel, gains in excess of 1.5 dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (46, 32), (81, 64), and (148, 128) shortened Imai-Kamiyanagi codes. Copyright © 2012 by the IETE.
Soft decision decoding of Davydov-Tombak codes using a parity check tree
(2010) Prashantha, Kumar, H.; Shripathi, Acharya U.; Rajesh, Shetty, K.; Shankarananda, B.
Davydov and Tombak have designed an excellent single error correction-double error detection (SEC-DED) code that appears to be more capable of detecting triple and quadruple errors than the conventional Hamming SEC-DED codes. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. A new approach to soft decision decoding of Davydov-Tombak codes using a parity check tree associated with the Tanner graph is presented. For the AWGN channel, gains in excess of 1.6dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (40, 33), (37, 30), (35, 28) and (72, 64) Davydov-Tombak codes. �2010 IEEE.
Soft decision decoding of Davydov-Tombak codes using a parity check tree
(2010) Prashantha Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
Davydov and Tombak have designed an excellent single error correction-double error detection (SEC-DED) code that appears to be more capable of detecting triple and quadruple errors than the conventional Hamming SEC-DED codes. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. A new approach to soft decision decoding of Davydov-Tombak codes using a parity check tree associated with the Tanner graph is presented. For the AWGN channel, gains in excess of 1.6dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (40, 33), (37, 30), (35, 28) and (72, 64) Davydov-Tombak codes. Â©2010 IEEE.
Synthesis of BCH codes for enhancing data integrity in flash memories
(2010) Rajesh, Shetty, K.; Shripathi, Acharya U.; Prashantha, Kumar, H.; Shankarananda, B.
Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. �2010 IEEE.
Synthesis of BCH codes for enhancing data integrity in flash memories
(2010) Rajesh Shetty, K.; Sripati, U.; Prashantha Kumar, H.; Shankarananda, B.
Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. Â©2010 IEEE.