Browsing by Author "Rajesh Shetty, K."

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Design and construction of BCH codes for enhancing data integrity in multi level flash memories
(Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.
Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.
Enhancing the error-correcting capability of imai-kamiyanagi codes for data storage systems by adopting iterative decoding using a parity check tree
(2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
A novel low-complexity, soft decision technique which allows the decoding of distance-5 double error-correcting Imai-Kamiyanagi codes by using a parity check tree associated with the Tanner graph is proposed. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. For the AWGN channel, gains in excess of 1.5 dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (46, 32), (81, 64), and (148, 128) shortened Imai-Kamiyanagi codes. Copyright © 2012 by the IETE.
High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices
(2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.
In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application. © 2012 Taylor & Francis.
Soft decision decoding of Davydov-Tombak codes using a parity check tree
(2010) Prashantha Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
Davydov and Tombak have designed an excellent single error correction-double error detection (SEC-DED) code that appears to be more capable of detecting triple and quadruple errors than the conventional Hamming SEC-DED codes. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. A new approach to soft decision decoding of Davydov-Tombak codes using a parity check tree associated with the Tanner graph is presented. For the AWGN channel, gains in excess of 1.6dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (40, 33), (37, 30), (35, 28) and (72, 64) Davydov-Tombak codes. Â©2010 IEEE.
Soft decision Fano decoding of block codes over discrete memoryless channel using tree diagram
(2012) Prashantha Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Setty Shankarananda, B.
A novel low complexity soft decision technique which allows the decoding of block codes with tree structure is proposed. These codes are shown to have a convenient tree structure that allows Fano decoding techniques to be used to decode them. The Fano algorithm searches through the tree structure of the block code for a path which has the optimal value of the Fano metric function. When a new candidate codeword is found, an optimality check is performed on it by using the threshold. If checked successfully, the candidate codeword is the most likely codeword and the search stops. The basic idea of this approach is to achieve a good error performance progressively in a minimum number of steps. For each decoding step, the error performance is tightly bounded and the decoding is terminated at the stage where either optimum or near optimum error performance is achieved. As a result, more flexibility in the trade off between performance and decoding complexity is provided. Some examples of the tree construction and the soft decision Fano decoding procedure are discussed. © 2012 FEI STU.
Synthesis of BCH codes for enhancing data integrity in flash memories
(2010) Rajesh Shetty, K.; Sripati, U.; Prashantha Kumar, H.; Shankarananda, B.
Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. Â©2010 IEEE.