Browsing by Author "Parane, K."

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An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks
(Birkhauser, 2020) Prabhu Prasad, B.M.; Parane, K.; Talawar, B.
In multi-processor system-on-chips, on-chip interconnection plays a significant role. The type of on-chip architecture being used in an application decides the performance of that application. Hence, a quick and versatile network-on-Chip (NoC) simulator, particularly for the larger designs, is essential to explore and find the best suitable NoC configuration for individual applications. An FPGA-based NoC simulation framework has been proposed in this work. The crossbar switch of the NoC router with buffers and five ports has been embedded in the wide multiplexers of the DSP48E1 slices. The distinctive feature of dynamic mode functionality of the DSP48E1 slices every clock cycle depending on the control signals of multiplexer plays a crucial role in incorporating the crossbar functionality. A substantial decrease in the configurable logic blocks (CLBs) utilization of NoC topologies on the FPGA has been observed by embedding the functionality of the crossbar on the DSP48E1 slices. Since there is a reduction in the use of CLB resources employing the crossbar based on DSP48E1, topologies of larger sizes can be simulated. 6 × 6 Mesh topology with the DSP crossbar implementation consumes 36% fewer lookup tables (LUTs) and 40% fewer flip flops than the Mesh topology with CLB-based crossbar implementation. 41% fewer LUTs and 23% fewer slices are consumed by the proposed work with respect to the state-of-the-art CONNECT NoC generation tool. Compared to DART, a reduction of 86% and 80% in LUTs and slices has been observed with respect to the proposed work. Hoplite-DSP implements the unidirectional Torus topology with no buffers considering the deflective routing algorithm. The proposed work targets Mesh-based topologies with buffers and bidirectional ports with XY and look-ahead routing algorithms. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.
Analysis of cache behaviour and software optimizations for faster on-chip network simulations
(Springer, 2019) Prasad, B.M.P.; Parane, K.; Talawar, B.
Fast simulations are critical in reducing time to market in chip multiprocessors and system-on-chips. Several simulators have been used to evaluate the performance and power consumed by network-on-chips (NoCs). To speedup the simulations, it is necessary to investigate and optimize the hotspots in the simulator source code. Among several simulators available, Booksim2.0 has been chosen for the experimentation as it is being extensively used in the NoC community. In this paper, the cache and memory system behavior of Booksim2.0 have been analyzed to accurately monitor input dependent performance bottlenecks. The measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having the least misses has been identified. To further reduce the cache misses, software optimization techniques such as removal of unused functions, loop interchanging and replacing post-increment operator with pre-increment operator for non-primitive data types have been employed. The cache misses were reduced by 18.52%, 5.34% and 3.91% by employing above technology respectively. Thread parallelization and vectorization have been employed to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93× and 3.97× were observed for the Mesh topology with 30 × 30 network size by employing thread parallelization and vectorization respectively. © 2019, The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden.
Cache analysis and software optimizations for faster on-chip network simulations
(2016) Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.
Fast simulations are critical in reducing time to market in CMPs and SoCs. Several simulators have been used to evaluate the performance and power consumed by Network-on-Chips. Researchers and designers rely upon these simulators for design space exploration of NoC architectures. Our experiments show that simulating large NoC topologies take hours to several days for completion. To speedup the simulations, it is necessary to investigate and optimize the hotspots in simulator source code. Among several simulators available, we choose Booksim2.0, as it is being extensively used in the NoC community. In this paper, we analyze the cache and memory system behaviour of Booksim2.0 to accurately monitor input dependent performance bottlenecks. Our measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having least misses has been identified. We also employ thread parallelization and vectorization to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93� and 3.97� were observed for the Mesh topology with 30 � 30 network size by employing thread parallelization and vectorization respectively. � 2016 IEEE.
Cache analysis and software optimizations for faster on-chip network simulations
(Institute of Electrical and Electronics Engineers Inc., 2016) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
Fast simulations are critical in reducing time to market in CMPs and SoCs. Several simulators have been used to evaluate the performance and power consumed by Network-on-Chips. Researchers and designers rely upon these simulators for design space exploration of NoC architectures. Our experiments show that simulating large NoC topologies take hours to several days for completion. To speedup the simulations, it is necessary to investigate and optimize the hotspots in simulator source code. Among several simulators available, we choose Booksim2.0, as it is being extensively used in the NoC community. In this paper, we analyze the cache and memory system behaviour of Booksim2.0 to accurately monitor input dependent performance bottlenecks. Our measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having least misses has been identified. We also employ thread parallelization and vectorization to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93Ã— and 3.97Ã— were observed for the Mesh topology with 30 Ã— 30 network size by employing thread parallelization and vectorization respectively. Â© 2016 IEEE.
Design of an adaptive and reliable network on chip router architecture using FPGA
(2019) Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.
We propose an adaptive, low cost, reliable and high performance router implemented based on a conventional two stage pipeline. The proposed Adaptive routing operates in adaptive mode as soon as the congestion is detected in network. We employ fault tolerant strategies for different components of routers such as input buffer, route compute unit, virtual channel allocation, switch allocation, and crossbar unit. The proposed router architecture differs from existing reliable routers, our implementation maintains the performance of fault tolerance router under massive network workloads by influencing the features of a crossbar, routing algorithm and router pipeline optimization. Our designed router is highly reliable than current fault receptive routers such as Wang[1], Vicis[2], BulletProof[3], RoCo[4] and Poluri[5]. The average latency is reduced by 0.69% and increased by 2.0% compared to fault tolerant and conventional router. � 2019 IEEE.
Design of an adaptive and reliable network on chip router architecture using FPGA
(Institute of Electrical and Electronics Engineers Inc., 2019) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
We propose an adaptive, low cost, reliable and high performance router implemented based on a conventional two stage pipeline. The proposed Adaptive routing operates in adaptive mode as soon as the congestion is detected in network. We employ fault tolerant strategies for different components of routers such as input buffer, route compute unit, virtual channel allocation, switch allocation, and crossbar unit. The proposed router architecture differs from existing reliable routers, our implementation maintains the performance of fault tolerance router under massive network workloads by influencing the features of a crossbar, routing algorithm and router pipeline optimization. Our designed router is highly reliable than current fault receptive routers such as Wang[1], Vicis[2], BulletProof[3], RoCo[4] and Poluri[5]. The average latency is reduced by 0.69% and increased by 2.0% compared to fault tolerant and conventional router. Â© 2019 IEEE.
FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
(2018) Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.
In this paper, we present fast and param-eterized FPGA based Network-on-Chip (NoC) simu-lation acceleration framework with automated HDL generation engine. The framework supports the NoC architecture design parameters such as topology, rout-ing algorithms, link width, buffer size, flow control and traffic patterns. The parameterized, high perfor-mance and lightweight nature of proposed NoC based framework makes the ideal choice for NoC research studies. The Mesh based topologies have been con-sidered for the experimentation purpose. A congestion aware adaptive routing has been proposed along with the conventional XY routing. Also, parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on the NoC behavior. The adaptive routing algorithm for Mesh based topologies has negligible FPGA area overhead compared to the conventional XY routing. Employing the adaptive routing algorithm, the average packet latency is reduced by 55 % under transpose traffic pattern when compared to the XY routing algorithm. The speedup of 2548x has been observed compared to Booksim software simulator. The proposed framework is 2.54x and 25x times faster compared to CONNECT and DART FPGA based simulators respectively. � 2018 IEEE.
FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
(Institute of Electrical and Electronics Engineers Inc., 2018) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
In this paper, we present fast and param-eterized FPGA based Network-on-Chip (NoC) simu-lation acceleration framework with automated HDL generation engine. The framework supports the NoC architecture design parameters such as topology, rout-ing algorithms, link width, buffer size, flow control and traffic patterns. The parameterized, high perfor-mance and lightweight nature of proposed NoC based framework makes the ideal choice for NoC research studies. The Mesh based topologies have been con-sidered for the experimentation purpose. A congestion aware adaptive routing has been proposed along with the conventional XY routing. Also, parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on the NoC behavior. The adaptive routing algorithm for Mesh based topologies has negligible FPGA area overhead compared to the conventional XY routing. Employing the adaptive routing algorithm, the average packet latency is reduced by 55 % under transpose traffic pattern when compared to the XY routing algorithm. The speedup of 2548x has been observed compared to Booksim software simulator. The proposed framework is 2.54x and 25x times faster compared to CONNECT and DART FPGA based simulators respectively. Â© 2018 IEEE.
FPGA friendly NoC simulation acceleration framework employing the hard blocks
(Springer, 2021) Prasad, B.M.P.; Parane, K.; Talawar, B.
A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures. © 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH, AT part of Springer Nature.
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
(2019) Prabhu, Prasad, B.M.; Parane, K.; Talawar, B.
An FPGA based Network on Chip (NoC) simulation acceleration framework is presented in this paper. The functionality of the crossbar switch of the NoC router is embedded in the hard multiplexers of the Xilinx DSP48E1 slices. A significant reduction in the soft logic (LUT+FF) utilization of the FPGA implementation of the 6 � 6 Torus topology has been observed by employing the hard multiplexers of the DSP48E1 slices in the proposed work. DSP based crossbar implementation of the 6 � 6 Torus topology consumes 38% fewer LUTs and 45% fewer FFs than the LUT based crossbar implementation. 35% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 76% fewer LUTs compared to the state-of-the-art CONNECT NoC generation tool. Buffered, bi-directional Torus topology with XY routing has been considered in the proposed DSP based implementation compared to the Hoplite-DSP which implements the bufferless, unidirectional Torus topology with deflective routing algorithm. The proposed framework achieves the speed up of 2.02� and 2.9� with respect to the LUT only and the CONNECT NoCs. � 2019 IEEE.
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
(Institute of Electrical and Electronics Engineers Inc., 2019) Prabhu Prasad, B.M.; Parane, K.; Talawar, B.
An FPGA based Network on Chip (NoC) simulation acceleration framework is presented in this paper. The functionality of the crossbar switch of the NoC router is embedded in the hard multiplexers of the Xilinx DSP48E1 slices. A significant reduction in the soft logic (LUT+FF) utilization of the FPGA implementation of the 6 Ã— 6 Torus topology has been observed by employing the hard multiplexers of the DSP48E1 slices in the proposed work. DSP based crossbar implementation of the 6 Ã— 6 Torus topology consumes 38% fewer LUTs and 45% fewer FFs than the LUT based crossbar implementation. 35% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 76% fewer LUTs compared to the state-of-the-art CONNECT NoC generation tool. Buffered, bi-directional Torus topology with XY routing has been considered in the proposed DSP based implementation compared to the Hoplite-DSP which implements the bufferless, unidirectional Torus topology with deflective routing algorithm. The proposed framework achieves the speed up of 2.02Ã— and 2.9Ã— with respect to the LUT only and the CONNECT NoCs. Â© 2019 IEEE.
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
(2019) Prabhu, P.B.M.; Parane, K.; Talawar, B.
The hard multiplexers of the Xilinx DSP48E1 slices have been employed to support the functionality of crossbar switch of the buffered five port Network-on-Chip (NoC) routers. This is possible due to the dynamic mode operation of the DSP48E1 slices per clock cycle based on the multiplexer control signals. As a result of this, a significant reduction in the soft logic (LUT+FF) utilization of the FPGA implementation of the 6� 6 Mesh topology has been observed. DSP based crossbar implementation of the 6� 6 Mesh topology consumes 36% fewer LUTs and 40% fewer FFs than the LUT based crossbar implementation. 38% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 41% fewer LUTs compared to the state-of-the-art CON-NECT NoC generation tool. The latency reductions of 31% and 38% have been achieved by the proposed DSP48E1 based crossbar implementation over the LUT crossbar implementation of 8� 8 Mesh topology under the Uniform and Transpose traffic patterns. Also, the proposed DSP48E1 based implementation achieves the saturation throughput improvements of 1.4� and 1.6� over the LUT based implementation under Uniform and Transpose traffic patterns respectively. � 2019 IEEE.
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
(IEEE Computer Society help@computer.org, 2019) Prabhu, P.B.M.; Parane, K.; Talawar, B.
The hard multiplexers of the Xilinx DSP48E1 slices have been employed to support the functionality of crossbar switch of the buffered five port Network-on-Chip (NoC) routers. This is possible due to the dynamic mode operation of the DSP48E1 slices per clock cycle based on the multiplexer control signals. As a result of this, a significant reduction in the soft logic (LUT+FF) utilization of the FPGA implementation of the 6Ã— 6 Mesh topology has been observed. DSP based crossbar implementation of the 6Ã— 6 Mesh topology consumes 36% fewer LUTs and 40% fewer FFs than the LUT based crossbar implementation. 38% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 41% fewer LUTs compared to the state-of-the-art CON-NECT NoC generation tool. The latency reductions of 31% and 38% have been achieved by the proposed DSP48E1 based crossbar implementation over the LUT crossbar implementation of 8Ã— 8 Mesh topology under the Uniform and Transpose traffic patterns. Also, the proposed DSP48E1 based implementation achieves the saturation throughput improvements of 1.4Ã— and 1.6Ã— over the LUT based implementation under Uniform and Transpose traffic patterns respectively. Â© 2019 IEEE.
Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation
(Institute of Electrical and Electronics Engineers Inc., 2021) Prabhu Prasad, B.M.; Parane, K.; Talawar, B.
Due to their hierarchical structure, Binary Tree (BTree) topology can be employed in Network-on-Chip (NoC) applications. Because of its lower bisection bandwidth, the performance degradation is observed in communication intensive applications. The Fat tree topology has been proposed to overcome the disadvantages of the BTree topology. But, the complexity of the Fat Tree topology's router becomes more complicated as we move towards the root node of the tree and occupying a huge amount of hardware resources compared to the BTree variant. Instead of going for Fat Tree topology, the number of hops taken by a packet in the BTree topology can be reduced by introducing new links in the network with an increase in the bisection bandwidth. In this work, we propose a variant of BTree topology called Hy-BTree by introducing additional links at the intermediate levels of the network to reduce the number of hops taken for the communication. The proposed design is implemented on the FPGA and compared with the other topologies from state-of-the-art the FPGA based NoC architectures. A reduction in average latency and an improvement in throughput have been observed in Hy-BTree with respect to the BTree network with negligible overhead. Â© 2021 IEEE.
Hybrid Deep Learning-Based Potato andÂ Tomato Leaf Disease Classification
(Springer Science and Business Media Deutschland GmbH, 2024) Patil, M.A.; Manur, M.; Laxuman, C.; Parane, K.; Dodamani, B.M.; Sunkad, G.
Predicting potato and tomato leaf disease is vital to global food security and economic stability. Potatoes and tomatoes are among the most important staple crops, providing essential nutrition to millions worldwide. However, many tomato and potato leaf diseases can seriously reduce food productivity and yields. We are proposing a hybrid deep learning model that combines optimized CNN (OCNN) and optimized LSTM (OLSTM). The weight values of LSTM and CNN models are optimized using the modified raindrop optimization (MRDO) algorithm and the modified shark smell optimization (MSSO) algorithm, respectively. The OCNN model is used to extract potato leaf image features and then fed into the OLSTM model, which handles data sequences and captures temporal dependencies from the extracted features. Precision, recall, F1-score, and accuracy metrics are used to analyze the output of the proposed OCNN-OLSTM model. The experimental performance is compared without optimizing the CNN-LSTM model, individual CNN and LSTM models, and existing MobileNet and ResNet50 models. The presented model results are compared with existing available work. We have received an accuracy of 99.25% potato and 99.31% for tomato. Â© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.
Internet-of-things and mobile application based hybrid model for controlling energy system
(Springer Science and Business Media B.V., 2021) Patil, M.A.; Parane, K.; Poojara, S.; Patil, A.
The Internet-of-Things (IoT) aims to combines physical objects in the world under a common infrastructure, it gives not only control of things, but also notify the state of the things. The automation for power saving based on the IoT has great business potential. The serious concern about the wastage of energy and this paper proposes an innovative hybrid method for automation system to reduce the wastage of power. The proposed hybrid method allows users to control and operate the electrical appliances manually or automatically. In automatic mode appliances are controlled through passive infrared (PIR) sensors and in manual mode appliances are controlled using android application. The developed system is deployed and tested in Laboratory, where it is used to control the electrical appliances such as, fans and tube lights. The usage of electricity is monitored and it is observed that the system reduced electrical bill of the laboratory by 24%. Finally, we have made a comparative analysis against existing system and it shows that the proposed hybrid system is better as compared to the existing systems. © 2021, Bharati Vidyapeeth's Institute of Computer Applications and Management.
LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
(Association for Computing Machinery acmhelp@acm.org, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks. © 2020 Association for Computing Machinery.
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
(Springer, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53× and 0.1× higher saturation throughput under nearest neighbor traffic compared to uniform random traffic. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.
Smart Attendance Management System using IoT
(Institute of Electrical and Electronics Engineers Inc., 2022) Patil, M.A.; Parane, K.; Sivaprasad, D.D.; Poojara, S.; Lamani, M.R.
Taking student attendance is mandatory in an educational organization, and maintaining those attendance plays a vital role. The conventional way of taking student attendance in any institution is time-consuming and challenging, because in the conventional procedure taking attendance/Roll call is performed manually by calling student names as per their roll numbers and marking 'absent(A)' or 'present(P)' on the attendance/logbook accordingly in every class per day. To improve teaching efficiency/teaching time in classrooms by reducing the time required for Roll call's, we have proposed a biometric student attendance system based on IoT. The proposed system records students' attendance using the facial-based biometric system and stores the attendance details on the server through the internet. In this system, the Raspberry pi camera captures the student face images and compares them with the stored images in the database. If the captured image is comparable with the stored image, then the student's attendance is recorded on the remote server as a present(P) in class; otherwise, attendance is recorded as absent (A). The developed system has been tested for sample classes, and the results proved that the system is simple, cost-effective, and portable for managing students' attendance. Â© 2022 IEEE.
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA
(2018) Sangeetha, G.S.; Radhakrishnan, V.; Prasad, P.; Parane, K.; Talawar, B.
Networking On Chips is now becoming an extremely important part of the present and future of electronic technology. It is extensively used in Multiprocessor System-on-Chips and in Chip Multiprocessors. Using an NoC, the backend wiring involved has drastically reduced in an SoC. Further, SoCs with NoC interconnect operates at a higher operating frequency, mainly because the hardware required for switching and routing are simplified. The NoC researchers have relied on simulators based on performance and power to study the different factors of NoC such as algorithm in place, the topology, the buffer management and location schemes, the flow control and routing among others. In this paper, we present a trace-driven NoC architecture that gives the user access to realistic details about the resource utilization of NoC architectures and their individual components. This includes exploration of various design decision parameters of NoC by modeling them on a FPGA. The paper also presents the performance of these architectures by conducting trace-driven simulations using benchmarks like PARSEC. Different topologies are considered for experimentation purposes with different routing algorithms. � 2018 IEEE.