Browsing by Author "Naik, D.N."

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A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems
(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.
In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023
An artificial bridge circuit approach between two biological neurons using nanoscale topologies towards paralytic disorders
(Elsevier Ltd, 2023) Haque, M.N.; Gorre, P.; Naik, D.N.; Kumar, S.; Al-Shidaifat, A.; Song, H.
The advent of Nanoscale IC technology towards pulse-based neural systems reactivates the dead nervous about restoring the functionality of paralytic disorders. This work reports in first time a design of a novel CMOS biological neuron system, which replaces a dead neuron between two neurons to restore communication in paralyzed individuals. The work binds into three stages: design of a spiking leaky Integrator and Fire (LIF) neuron with refractory period mechanisms, which achieves a low power consumption of 2.4 μW, in the first stage; an adaptive homeostatic synapse with short and long-term spike plasticity, that reconfigure the spiking neuron networks of multichannel sensor electrodes to record the electric signal from the active cell as second stage; the final stage presents a low-power common source current reuse regulated cascode (CS-CR-RGC) TIA for amplifying the weak synapse current signal, which achieves a high gain of 135.71 dBΩ with an optimized noise performance of 0.19 pA/Hz. The entire work is designed and implemented using a CMOS 65 nm commercial process that occupies a die area of 400 μm × 120 μm. © 2023
An Ultra-low Noise, Highly Compact Implantable 28 nm CMOS Neural Recording Amplifier
(Institute of Electronics Engineers of Korea, 2024) Akuri, N.G.; Naik, D.N.; Kumar, S.; Song, H.; Kar, A.
An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 fV/√Hz at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 µW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems. © 2024, Institute of Electronics Engineers of Korea. All rights reserved.
Design of Power Combiner and Power Divider at Ku Frequency Band Applications
(Institute of Electrical and Electronics Engineers Inc., 2023) Kumar, B.S.; Gorre, P.; Babu, B.R.; Samantaray, A.K.; Naik, D.N.; Kumar, S.
This paper presents the design of a Ku band power combiner and divider, operating within the frequency range of 12 GHz to 16 GHz. The power combiner achieves S(1,1) values of -23.17 dB, -19.47 dB, and -20.97 dB at 13 GHz, 13.87 GHz, and 14.77 GHz and S(1,2) values of -11.012dB at 13.98 GHz and S(1,3) value of -12.470 dB at 14.01 GHz and S(2,2) values of - 37.028dB at 13.28GHz respectively. Meanwhile, the power divider achieves S(1,1) values of -40 dB and -33 dB at 12.8 GHz and 13.8GHz and S(1,2) values of -13.173 dB at 13.02GHz and S(1,3) values of -15.590 dB at 13.02GHz and S(2,2) value of -21.744dB at 12.98GHz and S(2,2) value of -17.567 dB at 14.98 GHz respectively. The substrate employed is a 1.6mm thick FR-4 material. Â© 2023 IEEE.
Performance Analysis of Novel Graphene Process Low-Noise Amplifier with Multi-stage Stagger-Tuned Approach over D-band
(Springer, 2024) Nandini, P.; Naik, D.N.; Gorre, P.; Gupta, M.P.; Kumar, S.; Al-Shidaifat, A.; Song, H.
This work reports an ultra-low noise, multi-stage stagger-tuned low-noise amplifier (MS-ST-LNA) over the D-band performance and achieves a best trade-off between noise, bandwidth, and gain parameters. The ultra-low-noise is achieved in three ways: First, the high-gain 3-stage stagger tuned amplifier (STA) realizes a 3X gain compared to the conventional single-stage amplifier, which sets a low floor noise. Second, the stagger-tuned amplifier achieves 1.6 times lower noise than the traditional single-stage amplifier. Finally, the stagger tune realizes a high-order transfer function, which mitigates the high-frequency noise. The full LNA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using a 0.065-?m commercial process, occupying an area of 0.21 mm2. The proposed design achieves an optimum performance: a maximum measured gain of 20.5 dB and a minimum noise figure (NF) of 4.2 dB over 123.7 to 162.5 GHz. The proposed LNA consumes ultra-low power consumption of 21.3 mW under the power supply of 1.2 V. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.