Browsing by Author "Manukrishna, V.R."

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    Analysis of the non-monotonic dependence of FOM of β-Ga2O3based Junctionless Field Effect Transistor on doping profile linearity in the drift region
    (Institute of Electrical and Electronics Engineers Inc., 2024) Manukrishna, V.R.; Nikhil, K.S.
    In this work, the impact of variation of drift doping profile on the breakdown voltage and ON state power figure of merit (PFOM) of Variable Drift Doped Lateral β -Ga2O3Field Effect Transistor (VDDL-Ga2O3FET) has been reported. The variable lateral doping(VLD) technique was developed with an aim of attaining the minimum surface electric field through a drift region that is non-uniformly doped. In this work five devices namely Device A, Device B, Device C, Device D and Device E are simulated using synopsys sentaurus TCAD after applying VLD technique. The doping under source edge,gate region and drain edge are kept constant in all five devices. The region from gate edge to drain edge is divided into 2,3,4,5 and 10 in Device A, Device B, Device C, Device D and Device E respectively and variable doping is applied such a way that the concentration gradient between adjacent regions reduces as the number of regions increases. The TCAD simulation shows that Device C has maximum secondary breakdown voltage of 1353V and Device E gives maximum PFOM of 0.119MW/cm. Further investigation performed on critical electric field and impact ionization are in alignment with the results. © 2024 IEEE.
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    Improvement in Breakdown Voltage of Junctionless Power Transistor with Ga2O3 RESURF region
    (Institute of Electrical and Electronics Engineers Inc., 2023) Manukrishna, V.R.; Nikhil, K.S.
    From the recent reported studies, it is clear that Ga2O3 can offer higher breakdown voltage due to its higher bandgap. However, Ga2O3 based power devices are having challenges like low carrier concentration and less electron mobility. In this article, a Junctionless Enhancement mode Field Effect Transistor (FET) with Ga2O3 REduced SURface Field (RESURF) is proposed. The introduction of n-Type Ga2O3 RESURF region between gate and drain region improves the breakdown voltage. The asymmetric gate structure further enhances the breakdown voltage by delaying the attainment of critical electric field. The variation of on resistance (RON) for varying the length of RESURF region (Lr) is also investigated. Junctionless FET with Ga2O3 RESURF has shown large potential for high power integrated circuit applications. © 2023 IEEE.
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    INVESTIGATION OF THE IMPACT OF BURIED OXIDE LAYER IN UID LAYER AND CHANNEL REGION ON THE BREAKDOWN VOLTAGE AND THE THRESHOLD VOLTAGE OF β-GALLIUM OXIDE BASED POWER FETS
    (American Society of Mechanical Engineers (ASME), 2025) Manukrishna, V.R.; Nikhil, K.S.
    A ß-Ga2O3-based field-effect transistor with a buried oxide (BOX) layer is proposed for high-voltage applications such as electric vehicles and power ICs. In the proposed structure, the BOX layer is strategically incorporated within the channel region rather than extending into the unintentionally doped (UID) ß-Ga2O3 region. This placement effectively modulates the distribution of the electric field, mitigating the crowding of the peaK electric field near the drain side, and significantly improving the breaKdown voltage. The BOX layer, composed of silicon dioxide (SiO2), introduces additional capacitance, enhancing the electrostatic control of the gate over the channel. However, TCAD simulations reveal that variations in the thicKness of the BOX layer have minimal impact on the threshold voltage (Vtℎ), indicating that the dominant factors governing Vtℎ remain primarily associated with doping concentration and gate worK function. An empirical expression for the breaKdown voltage and an analytical expression for the threshold voltage, which incorporates the thicKness of the BOX layer, are derived and validated using TCAD test vectors. The redistribution of the electric field reduces impact ionization, enhances carrier transport, and improves overall device reliability, maKing the BOX-integrated JLFET a promising candidate for next-generation high-power and high-voltage electronics. © © 2025 by ASME.
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    Modeling of ?-Ga2O3 based double gate drain extended junction less FET and its parameter extraction methodology
    (Institute of Physics, 2025) Manukrishna, V.R.; Nikhil, K.S.
    A static current model of ?—Gallium Oxide (?-Ga2O3) based double gate drain extended junction less field effect transistor (DG-DeJLFET) is proposed. The model consists of two voltage-controlled current sources connected in series. One of the current sources accounts for the operation of the junction less field effect transistor whereas, the other takes care of the drift region current. The model is formulated by considering the mobility degradation caused by moderately elevated electric fields. A parameter extraction methodology for this model is also proposed by considering the dominance of certain parameters in the specific regions of operation. In general, the parameter extraction technique is based on the variation in the device current behavior at moderate electric fields. The proposed parameter extraction methodology is validated by comparing the results with the data obtained from the TCAD simulation. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.