Repository logo
Communities & Collections
All of DSpace
  • English
  • العربية
  • বাংলা
  • Català
  • Čeština
  • Deutsch
  • Ελληνικά
  • Español
  • Suomi
  • Français
  • Gàidhlig
  • हिंदी
  • Magyar
  • Italiano
  • Қазақ
  • Latviešu
  • Nederlands
  • Polski
  • Português
  • Português do Brasil
  • Srpski (lat)
  • Српски
  • Svenska
  • Türkçe
  • Yкраї́нська
  • Tiếng Việt
Log In
Have you forgotten your password?
  1. Home
  2. Browse by Author

Browsing by Author "Lad, K.K."

Filter results by typing the first few letters
Now showing 1 - 2 of 2
  • Results Per Page
  • Sort Options
  • No Thumbnail Available
    Item
    A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops
    (IEEE Computer Society help@computer.org, 2018) Kuncham, S.S.; Gadiyar, M.; Sushmitha Din, K.; Lad, K.K.; Laxminidhi, L.
    The inability to sense the transitions in the input by conventional phase frequency detector (PFD) during the reset operation leads to blind zone, which reduces the acquisition speed and the detection range. The pull down network in proposed design is modified so as to eliminate the reset pulse for phase difference beyond the dead zone in order to have a full detection range and less cycle slippage. As the design gives the right polarity for phase differences close to ±2π, the acquisition time is reduced substantially. The Transfer characteristic of the PFD manifests an identical response. The PFD design is implemented in 180nm CMOS technology and consumes 1.36mW at an operating frequency of 1GHz. © 2018 IEEE.
  • Thumbnail Image
    Item
    A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops
    (2018) Kuncham, S.S.; Gadiyar, M.; Sushmitha, Din, K.; Lad, K.K.; Laxminidhi, T.
    The inability to sense the transitions in the input by conventional phase frequency detector (PFD) during the reset operation leads to blind zone, which reduces the acquisition speed and the detection range. The pull down network in proposed design is modified so as to eliminate the reset pulse for phase difference beyond the dead zone in order to have a full detection range and less cycle slippage. As the design gives the right polarity for phase differences close to �2?, the acquisition time is reduced substantially. The Transfer characteristic of the PFD manifests an identical response. The PFD design is implemented in 180nm CMOS technology and consumes 1.36mW at an operating frequency of 1GHz. � 2018 IEEE.

Maintained by Central Library NITK | DSpace software copyright © 2002-2026 LYRASIS

  • Privacy policy
  • End User Agreement
  • Send Feedback
Repository logo COAR Notify