Browsing by Author "Jagadish, D.N."
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Item A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications(Institute of Electrical and Electronics Engineers Inc., 2014) Jagadish, D.N.; Bhat, M.S.A low voltage and low power inverter based differential amplifier is presented. The input stage is fully differential in operation and the output stage employ class C inverter to enhance the gain. An on-chip body bias improves the slew rate performance. The amplifier is implemented in UMC 90 nm technology. With load capacitance of 100fF, the amplifier delivers DC gain of 81dB and unity gain bandwidth of 33.88MHz at 41° phase margin. For a dual power supply voltage of ±350mV, the quiescent current and power consumption are 2.37μA and 1.66μW respectively. The amplifier achieves a figure of merit of 2117. With the bulk of all the transistors slightly forward biased by a fixed bias potential, the power dissipation of 672nW and figure of merit of 5431 are achieved. © 2014 IEEE.Item A low-energy area-efficient dual channel SAR ADC using common capacitor array technique(Institute of Electrical and Electronics Engineers Inc., 2016) Reddy, N.S.; Jagadish, D.N.; Bhat, M.S.A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 μW and exhibits a FOM of 101.14 fJ/conversion step. © 2016 IEEE.Item Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC(2015) Jagadish, D.N.; Bhat, M.S.A low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array (CA) in comparison to other nonbinary capacitor array based SAR ADCs. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside CA, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. � 2014 IEEE.Item Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC(Institute of Electrical and Electronics Engineers Inc., 2014) Jagadish, D.N.; Bhat, M.S.A low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array (CA) in comparison to other nonbinary capacitor array based SAR ADCs. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside CA, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. © 2014 IEEE.Item Low energy and area efficient nonbinary capacitor array based successive approximation register analog-to-digital converter(2015) Jagadish, D.N.; Bhat, M.S.In this paper, we propose a low energy consumption and area efficient successive approximation register analogue-to-digital converter. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array in comparison to other nonbinary capacitor array based successive approximation register analogue-to-digital converters. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside capacitor array, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. Copyright � 2015 American Scientific Publishers All rights reserved.Item Low energy and area efficient nonbinary capacitor array based successive approximation register analog-to-digital converter(American Scientific Publishers, 2015) Jagadish, D.N.; Bhat, M.S.In this paper, we propose a low energy consumption and area efficient successive approximation register analogue-to-digital converter. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array in comparison to other nonbinary capacitor array based successive approximation register analogue-to-digital converters. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside capacitor array, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. © © 2015 American Scientific Publishers All rights reserved.Item A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications(2015) Jagadish, D.N.; Bhat, M.S.A low voltage and low power inverter based differential amplifier is presented. The input stage is fully differential in operation and the output stage employ class C inverter to enhance the gain. An on-chip body bias improves the slew rate performance. The amplifier is implemented in UMC 90 nm technology. With load capacitance of 100fF, the amplifier delivers DC gain of 81dB and unity gain bandwidth of 33.88MHz at 41� phase margin. For a dual power supply voltage of �350mV, the quiescent current and power consumption are 2.37?A and 1.66?W respectively. The amplifier achieves a figure of merit of 2117. With the bulk of all the transistors slightly forward biased by a fixed bias potential, the power dissipation of 672nW and figure of merit of 5431 are achieved. � 2014 IEEE.Item A low-energy area-efficient dual channel SAR ADC using common capacitor array technique(2016) Reddy, N.S.; Jagadish, D.N.; Bhat, M.S.A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18?m CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 ?W and exhibits a FOM of 101.14 fJ/conversion step. � 2016 IEEE.