Browsing by Author "Jagabar Sathik, M.J."

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    High gain active neutral point clamped seven-level self-voltage balancing inverter
    (Institute of Electrical and Electronics Engineers Inc., 2020) Jagabar Sathik, M.J.; Sandeep, N.; Blaabjerg, F.
    This brief presents a novel seven-level (7L) inverter topology for grid-connected renewable applications. It consists of ten active switches and one inner flying-capacitor unit forming a structure similar to conventional active neutral point clamped inverter. The proposed unique arrangement reduces the number of active, passive components and it does not require any sensor to balance the floating capacitor voltage, thereby reduces cost and complexity in the control system design. In addition, compared to major conventional 7L inverter topologies, the proposed topology is capable of boosting the input voltage by a factor of 1.5, thereby, eliminating the need for an intermediate boosting stage. In other words, it reduces the dc-link voltage requirement by 50%. To prove the advantage of the proposed topology over other recent topologies, a comparative study in terms of power components and cost is presented. The operation and performance of the proposed topology for various loading conditions are validated through experimental tests and measurements. © 2004-2012 IEEE.
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    Seven-level boosting active neutral point clamped inverter using cross-connected switched capacitor cells
    (Institution of Engineering and Technology jbristow@theiet.org, 2020) Jagabar Sathik, M.J.; Sandeep, N.; Almakhles, D.; Bhatnagar, K.; Yang, Y.; Blaabjerg, F.
    In this study, an active neutral point clamped-type boosting switched-capacitor multilevel inverter (SCMLI) with selfvoltage balancing capability is proposed. In the proposed topology, a novel switched capacitor cell is used, which has eightswitches and two diodes. The presented topology has reduced power component count with self-boosting and balancingabilities. The distinctive features of the proposed topology are highlighted and benchmarked against other recent 7L-SCMLItopologies. To validate the feasibility of the proposed topology, experimental tests are performed on a 1 kW prototype hardwaresetup. © 2020 The Institution of Engineering and Technology.