Browsing by Author "Herolli, P.K."

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    PVT compensated high selectivity low-power balun LNA for MedRadio communication
    (2018) KuppiReddy, V.R.; Herolli, P.K.; Baghini, M.S.
    A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-?m CMOS technology, the DC power consumption is 290 ?W under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 ?m 978 ?m. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10 . The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec. 2018, The Institution of Engineering and Technology.
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    PVT compensated high selectivity low-power balun LNA for MedRadio communication
    (Institution of Engineering and Technology journals@theiet.org, 2018) Vasudeva Reddy, V.R.; Herolli, P.K.; Shojaei Baghini, M.S.
    A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-?m CMOS technology, the DC power consumption is 290 ?W under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 ?m × 978 ?m. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec. © 2018, The Institution of Engineering and Technology.