Browsing by Author "Gunnam, S."

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    A Resolution Independent 2-Bits-per-Cycle SAR ADC
    (Institute of Electrical and Electronics Engineers Inc., 2014) Morakhia, A.; Gunnam, S.; Prakash, P.; Kudli, S.; Laxminidhi, T.
    This paper proposes a resolution independent architecture for SAR ADCs. The proposed architecture uses 2 bits per cycle conversion and is made independent of number of ADC bits. A 2-bit flash ADC is used to compute 2-bits in each iteration. The reference voltage across the resistor divider of the 2-bit flash ADC is changed in each iteration based on the 2-bits resolved in the previous iteration. The reference voltages for each iteration are generated using a pair of modified switched capacitor-based DACs. The new DAC architecture used in the proposed ADC can use the thermometric code output of the 2-bit flash ADC directly, avoiding the need for complex control circuitry. The dependency of DAC architecture on the ADC resolution, observed in conventional SAR ADCs, has been absorbed into the digital logic which is easy to design. The proposed architecture is validated using an 8 bit ADC designed in 0.25 μm CMOS process. © 2014 IEEE.
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    A Resolution Independent 2-Bits-per-Cycle SAR ADC
    (2015) Morakhia, A.; Gunnam, S.; Prakash, P.; Kudli, S.; Laxminidhi, T.
    This paper proposes a resolution independent architecture for SAR ADCs. The proposed architecture uses 2 bits per cycle conversion and is made independent of number of ADC bits. A 2-bit flash ADC is used to compute 2-bits in each iteration. The reference voltage across the resistor divider of the 2-bit flash ADC is changed in each iteration based on the 2-bits resolved in the previous iteration. The reference voltages for each iteration are generated using a pair of modified switched capacitor-based DACs. The new DAC architecture used in the proposed ADC can use the thermometric code output of the 2-bit flash ADC directly, avoiding the need for complex control circuitry. The dependency of DAC architecture on the ADC resolution, observed in conventional SAR ADCs, has been absorbed into the digital logic which is easy to design. The proposed architecture is validated using an 8 bit ADC designed in 0.25 ?m CMOS process. � 2014 IEEE.