Browsing by Author "Devarajan, H."

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    Design of an HV capacitor using the inherent advantage of charge simulation method and experimentations
    (2018) Devarajan, H.; Punekar, G.S.; Kishore, N.K.
    Standard capacitors form an important component of the measurement and instrumentation in the electrical laboratory. A high-voltage (HV) standard capacitor of 100 pF, 12 kV (rms) is designed using the charge simulation method (CSM). CSM is a semi-analytical method and it provides inherent advantage in designing a capacitor from the first principle. The capacitance is obtained from the magnitude of the simulating charges of the CSM-based model and the corresponding potential. The design details of HV standard capacitor are discussed along with the analysis of the potential and the electric stress distribution. The electric stress everywhere in the capacitor, which is designed, is assured to be <5 kV/cm, which was set as the limiting (maximum permissible) stress. The capacitance of the fabricated unit is measured in the HV laboratory. The CSM-based result of the capacitance of the designed HV capacitor agree well with the results of the laboratory experimental measurement. The inherent advantage of CSM in designing a capacitor is confirmed by comparing with the results of method of moments (MoM). The Institution of Engineering and Technology.
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    Design of an HV capacitor using the inherent advantage of charge simulation method and experimentations
    (Institution of Engineering and Technology journals@theiet.org, 2018) Devarajan, H.; Punekar, G.S.; Kishore, N.K.
    Standard capacitors form an important component of the measurement and instrumentation in the electrical laboratory. A high-voltage (HV) standard capacitor of 100 pF, 12 kV (rms) is designed using the charge simulation method (CSM). CSM is a semi-analytical method and it provides inherent advantage in designing a capacitor from the first principle. The capacitance is obtained from the magnitude of the simulating charges of the CSM-based model and the corresponding potential. The design details of HV standard capacitor are discussed along with the analysis of the potential and the electric stress distribution. The electric stress everywhere in the capacitor, which is designed, is assured to be <5 kV/cm, which was set as the limiting (maximum permissible) stress. The capacitance of the fabricated unit is measured in the HV laboratory. The CSM-based result of the capacitance of the designed HV capacitor agree well with the results of the laboratory experimental measurement. The inherent advantage of CSM in designing a capacitor is confirmed by comparing with the results of method of moments (MoM). © The Institution of Engineering and Technology.