Browsing by Author "Akuri, N.G."

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    An Ultra-low Noise, Highly Compact Implantable 28 nm CMOS Neural Recording Amplifier
    (Institute of Electronics Engineers of Korea, 2024) Akuri, N.G.; Naik, D.N.; Kumar, S.; Song, H.; Kar, A.
    An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 fV/√Hz at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 µW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems. © 2024, Institute of Electronics Engineers of Korea. All rights reserved.
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    High-Performance Graphene FET Integrated Front-End Amplifier Using Pseudo-resistor Technique for Neuro-prosthetic Diagnosis
    (SpringerOpen, 2022) Naik, J.D.; Gorre, P.; Akuri, N.G.; Kumar, S.; Al-Shidaifat, A.D.; Song, H.
    A complex analysis of spike monitoring in neuro-prosthetic diagnosis demands a high-speed sub-nanoscale transistors with an advanced device technologies. This work reports the high performance of Graphene field-effect transistor (GFET) based front-end amplifier (FEA) design for the neuro-prosthetic application. The 9 nm Graphene FET device is optimized by characterization of transconductance and drain current towards high sensitivity and small factor. The proposed GFET-based FEA with pseudo-resistor technique demonstrates very high-input impedance in Tera-ohms that nullify the input leakage current. Here, gain-bandwidth product and noise optimization of GFET FEA enhances the overall gain with negligible noise. The proposed design operates at low voltage, further reduces the power consumption, and achieves less chip area in sub-nano size so it could be more suitable for implantable devices. The GFET-based FEA architecture achieves an action potential spike of 1.4 µV while the local field potentials spike of 1.8 mV. The proposed architecture is implemented in Advanced Design System using the design kit of the GFET process. Power consumption of 3.14 µW is observed with a supply voltage of 0.9 V. The simulated and experimental results of the proposed design achieve an input impedance of 2 TΩ with excellent noise performance over a wideband of 13.85 MHz. The proposed work demonstrates better neural activity sensing when compared to the state-of-the-artwork, which could be highly beneficial for future neuroscientists. © 2022, The Korean BioChip Society.