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https://idr.nitk.ac.in/jspui/handle/123456789/14649
Title: | Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors |
Authors: | Bhat K.G. Laxminidhi T. Bhat M.S. |
Issue Date: | 2020 |
Citation: | Sadhana - Academy Proceedings in Engineering Sciences , Vol. 45 , 1 , p. - |
Abstract: | A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead. © 2020, Indian Academy of Sciences. |
URI: | https://doi.org/10.1007/s12046-020-01421-2 http://idr.nitk.ac.in/jspui/handle/123456789/14649 |
Appears in Collections: | 5. Miscellaneous Publications |
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